• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.292-295
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• 2004

The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1208-1211
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• 2008

We study the amorphous In-Ga-Zn-O thin-film transistors (TFTs) properties under monochromatic illumination ($\lambda=420nm$) with different intensity. TFT off-state drain current ($I_{DS_off}$) was found to increase with the light intensity while field effect mobility ($\mu_{eff}$) is almost unchanged; only small change was observed for sub-threshold swing (S). Due to photo-generated charge trapping, a negative threshold voltage ($V_{th}$) shift is also observed. The photofield-effect analysis suggests a highly efficient UV photocurrent conversion in a-IGZO TFT. Finally, a-IGZO mid-gap density-of-states (DOS) was extracted and is more than an order lower than reported value for a-Si:H, which can explain a good switching properties of the a-IGZO TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.186-189
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.595-596
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and low-temperature processes. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing which is high-resolution lithography technology using polydimethylsiloxane(PDMS) stamp. The OTFT array with dielectric layer and organic active semiconductor layers formed at room temperature or at a temperature tower than $40^{\circ}C$. The microcontact printing process using SAM(self-assembled monolayer) and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even nano size, and reduced the procedure by 10 steps compared with photolithography. Since the process was done in low temperature, there was no pattern transformation and bending problem appeared. It was possible to increase close packing of molecules by SAM, to improve electric field mobility, to decrease contact resistance, and to reduce threshold voltage by using a big dielecric.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.506-510
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• 2016

A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

• Carbon letters
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• v.21
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• pp.8-15
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• 2017

The thermoelectric Seebeck and Peltier effects of a single walled carbon nanotube (SWCNT) quantum dot nanodevice are investigated, taking into consideration a certain value of applied tensile strain and induced ac-field with frequency in the terahertz (THz) range. This device is modeled as a SWCNT quantum dot connected to metallic leads. These two metallic leads operate as a source and a drain. In this three-terminal device, the conducting substance is the gate electrode. Another metallic gate is used to govern the electrostatics and the switching of the carbon nanotube channel. The substances at the carbon nanotube quantum dot/metal contact are controlled by the back gate. Results show that both the Seebeck and Peltier coefficients have random oscillation as a function of gate voltage in the Coulomb blockade regime for all types of SWCNT quantum dots. Also, the values of both the Seebeck and Peltier coefficients are enhanced, mainly due to the induced tensile strain. Results show that the three types of SWCNT quantum dot are good thermoelectric nanodevices for energy harvesting (Seebeck effect) and good coolers for nanoelectronic devices (Peltier effect).

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.1071-1079
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• 2010

This paper describes the design and fabrication of a high-efficiency GaN HEMT(Gallium Nitride High-electron Mobility Transistor) Pallet power amplifier module for S-band phased array radar applications. Pallet amplifier module has a series 2-cascaded power amplifier and the final amplification-stage consists of balanced GaN HEMT transistor. In order to achieve high efficiency characteristic of pallet power amplifier module, all amplifiers are designed to the switching-mode amplifier. We performed with various PRF(Pulse Repetition Frequency) of 1, 10, 100 and 1000Hz at a fixed pulse width of $100{\mu}s$. In the experimental results, the output power, gain, and drain efficiency(${\eta}_{total}$) of the Pallet power amplifier module are 300W, 33dB, and 51% at saturated output power of 2.9GHz, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.155-158
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• 2007

Printed organic thin-film transistor(OTFT) to use as a switching device for an organic light emitting diode(OLED) were fabricated in the microcontact printing and direct printing processes at room temperature. The gate electrodes($5{\mu}m$, $10{\mu}m$, and $20{\mu}m$) of OTFT was fabricated using microcontact printing process, and source/drain electrodes ($W/L=500{\mu}m/5{\mu}m$, $500{\mu}m/10{\mu}m$, and $500{\mu}m/20{\mu}m$) was fabricated using direct printing process with hard poly(dimethylsiloxane)(h-PDMS) stamp. Printed OTFT with dielectric layer was formed using special coating system and organic semiconductor layer was ink-jet printing process. Microcontact printing and direct printing processes using h-PDMS stamp made it possible to fabricate printed OTFT with channel lengths down to $5{\mu}m$, and reduced the process by 20 steps compared with photolithography. As results of measuring he transfer characteristics and output characteristics of OTFT fabricated with the printing process, the field effect characteristic was verified.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.3
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• pp.55-64
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• 2013

In this paper, a new topology which can add a small reactor in series to a condenser-bank type reactive power compensator to limit current is proposed. And also the proposed topology can add or remove a power condenser safely without any addition of inrush-current suppression resistance. The proposed method tests variable resistance of the drain source of a switching device which is controlled by gate voltage in a two-way switch with a diode rectifier and FET switch. In other words, the proposed method is a inrush-current suppression method with the structure of variable resistance. In particular, the proposed method creates smooth current without any resonance in inrush-current as well as is not limited by the time of switch on and off.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.