• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.116-120
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• 2007

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that $I_{dark}\;is\;{\sim}10^{-13}\;A,\;I_{photo}\;is\;{\sim}10^{-9}\;A\;and\;I_{photo}/I_{dark}\;is\;{\sim}10^4$, respectively. In the case of a-Si:H TFT, it indicates that $I_{on}/I_{off}\;is\;10^6$, the drain current is a few ${\mu}A\;and\;V_{th}\;is\;2{\sim}4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 volts in ITO of photodiode and $70 {\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2273-2277
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• 2010

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.1
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• pp.1-9
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• 2007

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the Ka-band. The gate bias voltage is selected by frequency multiplier theory to maximize the third-order harmonic element ofthe fundamental LO frequency in the proposed mixer. The designed mixer has a gate mixer structure composed of a gate terminal input for the fundamental local signal ($f_{LO}$), RF signal (${RF}$) and a drain terminal output for the harmonic frequency ($3f_{LO}-f_{RF}$) respectively. The Ka-band harmonic mixer is designed and fabricated using a commercial GaAs MESFET device with a plastic package. The proposed mixer will provide a solution for the problems found in the high cost, complex circuitry in a conventional Ka-band mixer. The 33.5 GHz harmonic mixer has a -10 dB conversion gain by pumping 11.5 GHz LO with a +5 dBm level.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1281_1282
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• 2009

ICP-CVD를 이용하여 inverted staggered 구조를 갖는 미세결정 실리콘 (Nanocrystalline Silicon, nc-Si) 박막 트랜지스터(Thin Film Transistor, TFT)를 제작하였다. 또한, 소자의 특성과 전기적 안정성을 평가하였다. 실험 결과는 짧은 채널 길이를 갖는 nc-Si TFT가 긴 채널 길이의 소자보다 같은 드레인 전압 바이어스 하에서 덜 열화 됨을 알 수 있었다. 이는 드레인 전압 바이어스 하에서의 낮은 채널 캐리어 농도는 적은 defect state를 만들기 때문으로 짧은 채널 길이의 TFT가 긴 채널 길이의 TFT보다 $V_{TH}$ 열화가 적었다. 이러한 결과는 짧은 채널 길이의 nc-Si TFT가 디스플레이 분야에 있어 다양하게 응용될 것으로 기대된다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1301-1304
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• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.747-751
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• 2006

The hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) with copper as source and drain electrode has been fabricated to obtain its transfer characteristics and stressed with positive and negative bias to investigate the instability variation comparing to conventional MoW-Al based TFT device. The results show that there is no copper diffusion into active layer of a-Si:H TFT, even during the thermal process. In addition, a 15-inch XGA a Si:H TFT LCD display utilizing Cu as gate electrodes has been developed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.233-236
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• 2000

Polycrystalline Silicon Thin Film Transistors(Poly-Si TFT's), fabricated at temperature lower than $600^{\circ}C$ are now largely used in many applications, particularly in large area electrons. In this work, electrical stress effects on Poly-Si TFT's fabricated by Solid Phase Crystal(SPC) was investigated by measuring electric properities such as transfer and output characteristics, and channel conductance. Consequently, It is turned out that it should be noted the output characteristics, drain current and channel conductance, strongly degrade around origin.