• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.465-465
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• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.39-39
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• 2009

We fabricated p-channel TFTs based on poly Silicon. The 35nm thickness silicon dioxide layer structure got higher $I_{on}/I_{off}$ ratio, field-effect Mobility and output current than 10nm thickness. And 35nm layer showed low leakage current and threshold voltage. So, 35nm thickness silicon dioxide layer TFTs are faster reaction speed and lower power consumption than 10nm thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.159-161
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• 2007

We fabricated flexible OTFT-backplanes for the electrophoretic display(EPD). The OTFTs employed bottom contact structure on PEN substrate and used the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. Especially, we used PVA/Acryl double layers for passivation of backplane as well as for pixel dielectric layer between backplane and EPD panel. The OTFT-EPD panel worked successfully anddemonstrated to display some patterns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.19-24
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• 2004

In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. The device performance was characterized by DC and RF measurement. The fabricated 70 nm InGaAs/InAlAs MHEMTS with 70 ${\mu}{\textrm}{m}$ unit gate width and 2 fingers showed good DC and RF characteristics of Idss, max =228.6 mA/mm, gm =645 mS/mm, and fT =255 GHz, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.576-581
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• 2005

In this paper. the a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. High k gate dielectric is required for on-current, threshold voltage and breakdown characteristics of TFT Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_3N_4$. Ferroelectric increases on-current and decreases threshold voltage of TFT and also ran improve breakdown characteristics.$SrTiO_4$ thin film is deposited by e-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C\~600^{\circ}C$. Dielectric constant of ferroelectric is about 60-100 and breakdown field is about IMV/cm. In this paper, the TFT using ferroelectric consisted of double layer gate insulator to minimize the leakage current. a-SiN:H, a-Si:H (n-type a-Si:H) are deposited onto $SrTiO_3$ film to make MFNS(Metal/ferroelectric/a-SiN:H/a-Si:H) by PECVD. In this paper, TFR using ferroelectric has channel length of$8~20{\mu}m$ and channel width of $80~200{\mu}m$. And it shows that drain current is $3.4{\mu}A$at 20 gate voltage, $I_{on}/I_{off}$ is a ratio of $10^5\~10^8,\;and\;V_{th}$ is$4\~5\;volts$, respectively. In the case of TFT without having ferroelectric, it indicates that the drain current is $1.5{\mu}A$ at 20gate voltage and $V_{th}$ is $5\~6$ volts. If properties of the ferroelectric thin film are improved, the performance of TFT using this ferroelectric thin film can be advanced.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.41-44
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• 2022

In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al₂O₃/HfO₂ = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 10³ at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.