• Magazine of the Korean Society of Agricultural Engineers
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• v.39 no.4
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• pp.98-105
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• 1997

Compacted clay materials are often used to form barriers for waste disposal by means of landfill. The performance of clay barrier depends on its permeability characteristics under the site environments. The study discusses permeability characteristics of 4 types of permeants through a compacted clayey soil. Permeabilities are measured using the modified rigid-wall permeater and with water, PEG, Ethanol, and TCE, ranging 80 to 3.4 of dielectric constants. Results of the study are as follows : 1) Absolute permeabilities of Ethanol and TCE that their dielectric constants are lower than that of water are $K=1.0{\times} 10^{-12} cm^2$, and $5.8{\times} 10^{-12} cm^2$, respectively, that is, 1.67, and 9.67 times of permeability of water, respectively. Absolute permeability and dielectric constant of water are $K=6{\times} 10^{-13} cm^2$, and 80, respectively. 2) Changes in absolute permeability of Ethanol and TCE converge to a constant after 3.5 pore volume of permeant flows through the clay sample. This can be explained that diffuse double layer of clay is no longer reacted with permeants and contracted their pores. However there is no change in absolute permeability when water is used as a per-meant. 3) It is found that absolute permeability in reversely proportional to the value of dielectric constant of the permeants. Change in absolute permeability of the permeants with 40 or over of dielectric constant is not significant. However change in absolute permeability of the permeant with 30 or lower dielectric constant is abruptly increased. 4) A lower absolute permeability of PEG is found because of its high viscosity.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.194-201
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• 2010

We propose a frequency selective surface(FSS) using double split ring resonators(DSRRs) for isolation enhancement between CDMA and RFID. The structure consists of an outer SRR and an inner SRR, and the gaps are formed in the same direction. By properly adjusting the gap and line width, the resonant frequency and skirt characteristics can be adjusted without varying the unit cell size. The proposed structure has a different field distribution from that of an ordinary SRR for magneto-dielectric materials. One layer consists of $9{\times}9$ unit cells and the other layer was separated by 50 mm. To validate the simulation results, we fabricated the patch antenna and the FSSs, and the measured results show a good agreement with the simulated ones. The electrical size of the unit cell is $0.110\;{\lambda}{\times}0.110\;{\lambda}{\times}0.002\;{\lambda}$, and the size of the two layer FSS is $1.058\;{\lambda}{\times}1.058\;{\lambda}{\times}0.153\;{\lambda}$. The two layer FSS maintain gain in CDMA frequency and has 6.9 dB reduced gain in RFID frequency.

• The Korean Journal of Ceramics
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• v.1 no.1
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• pp.7-12
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• 1995

When a $Ta_O_5$ dielectric film is deposited on a bare silicon, the growth of $SiO_2$ at the $Ta_O_5$/Si interface cannot be avoided. Even though the $SiO_2$ layer is ultrathin (a few nm), it has great effects on the electrical properties of the capacitor. The concentration depth profiles of the ultrathin interfacial $SiO_2$ and $SiO_2/Si_3N_4$ layers were obtained using an Auger electron spectroscopy (AES) equipped with a cylindrical mirror analyzer (CMA). These AES depth profiles were quantitatively analyzed by comparing with the theoretical depth profiles which were obtained by considering the inelastic mean free path of Auger electrons and the angular acceptance function of CMA. The direct measurement of the interfacial layer thicknesses by using a high resolution cross-sectional TEM confirmed the accuracy of the AES depth analysis. The $SiO_2/Si_3N_4$ double layers, which were not distinguishable from each other under the TEM observation, could be effectively analyzed by the AES depth profiling technique.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.873-877
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• 2007

In order to apply a complex multilayer chip LC filter, this study has estimated the interfacial reaction and coupling properties of dielectric materials $Pb(Fe_{1/2}Nb_{1/2})O_3$ and Ni-Zn-Cu ferrite materials through low-temperature co-sintering (LTCS). PFN powders were fabricated using double calcinated at $700^{\circ}C$ and then $850^{\circ}C$. While the perovskite phase rate was found to be 91 %, after heat treatment at $900^{\circ}C$ for 6h, the perovskite phase rate and density exhibited a value of 100 % and 7.46$g/cm^3$, respectively. The PFN/Ni-Zn-Cu ferrite, PFN/CUO (or $Pb_2Fe_2O_5$) and ferrite/CuO (or $Pb_2Fe_2O_5$) were mechanically coupled through interfacial reactions after the specimen was co-sintered at $900^{\circ}C$ for 6 h. No intermediate layer exists for the mutual coupling reaction. This result indicates the possibility of low-temperature co-sintering without any interfacial reaction layer for a multilayer chip LC filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.19-24
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• 2004

In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. The device performance was characterized by DC and RF measurement. The fabricated 70 nm InGaAs/InAlAs MHEMTS with 70 ${\mu}{\textrm}{m}$ unit gate width and 2 fingers showed good DC and RF characteristics of Idss, max =228.6 mA/mm, gm =645 mS/mm, and fT =255 GHz, respectively.

• Journal of the Korean Ceramic Society
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• v.31 no.11
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• pp.1330-1336
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• 1994

Ta2O5 films were deposited on the p-Si(100) substrates by ECR-PECVD and annealed in O2 atmosphere. The thicknesses of Ta2O5/SiO2 layers were measured by an ellipsometer and a cross-sectional TEM. Annealing in O2 atmosphere enhanced the stoichiometry of the Ta2O5 film and reduced the impurity carbon content. Ta2O5 films were crystallized at the annealing temperatures above 75$0^{\circ}C$. The best leakage current characteristics and the maximum dielectric constant of Ta2O5/SiO2 film capacitor were observed in the specimen annealed at $700^{\circ}C$ and 75$0^{\circ}C$, respectively. The flat band voltage of the Al/Ta2O5/SiO2/p-Si MOS capacitor was varied in the range of -0.6~-1.6 V with the annealing temperature. The conduction mechanism in the Ta2O5 film, the variation of the effective oxide charge density with the annealing temperature, and the effective electric field distribution in the Ta2O5/SiO2 double layer were also discussed.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.41-44
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• 2022

In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al₂O₃/HfO₂ = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 10³ at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.8
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• pp.700-703
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• 2000

We investigated the improvement using a new patterned double twisted(PDT) vertical-alignment(VA) cell mode on a homeotropic alignment layer. Good voltage-transmittance curves for negative dielectric anisotropic nematic liquid crystal (NLC) using a new PDT-VA cell without a negative compensation film were obtained. The viewing angle of a new PDT-VA cell without a negative compensation film was sider than that of a conventional VA cell. Finally a few fabrication processes using a new PDT-VA cell mode can be achieved by only one-side rubbed substrate.