• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.107-108
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• 2006

In this work, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Bi_{3.25}La_{0.75}Ti_{3}O_{12}$ (BLT) ferroelectric film was fabricated by the sol-gel method. However, there have been serious problems in CMP in terms of repeatability and defects in patterned wafer. Especially, dishing & erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the lifetime of the semiconductor. Cross-sections of the wafer before and after CMP were examined by Scanning electron microscope(SEM). Process characteristics of non-dishing and erosion were investigated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• International Journal of CAD/CAM
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• 제11권1호
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• pp.18-26
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• 2011

This paper proposes a new solid-shape modeling system based on a lusterware-image illustration. The proposed method reconstructs a three dimensional solid shape from a set of rough sketches that are typically drawn in the early stages of the design process. The sketches do not have to be strictly accurate, and this tolerance to the roughness of the input sketches is one of the major advantages of the proposed method. The proposed system creates an initial shape based on the silhouette of the input lusterware-images. Then the user can edit the initial shape with intuitive cutting and dishing-up operations, which are based on sketching user interface. To achieve the goal, the system retains the geometric model with two representations: a point-set data and a volume data. This dual data structure allows the program to create an initial shape from the input images with little computational cost, and the user can apply cutting and dishing-up operations without substantially increasing computational and memory requirements. In this research, we have tested the proposed system by reconstructing solid models of some mechanical parts from rough sketches. The experimental results indicate that the proposed method is useful for the prototyping of a solid shape.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.37-41
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• 2012

Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 $SiO_2$와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.81-85
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• 2013

웨이퍼 적층 기술은 반도체 전 후 공정을 이용한 효과적인 방법으로 향후 3D 적층 시스템의 주도적인 발전방향이라고 할 수 있다. 웨이퍼 레벨 3D 적층 시스템을 제조하기 위해서는 TSV (Through Si Via), 웨이퍼 본딩, 그리고 웨이퍼 thinning의 단위공정 개발 및 웨이퍼 warpage, 열적 기계적 신뢰성, 전력전달, 등 시스템적인 요소에 대한 연구개발이 동시에 진행되어야 한다. 본 연구에서는 웨이퍼 본딩에 가장 중요한 역할을 하는 Cu CMP (chemical mechanical polishing) 공정에 대한 특성 분석을 진행하였다. 8인치 Si 웨이퍼에 다마신 공정으로 Cu 범프 웨이퍼를 제작하였고, Cu CMP 공정과 oxide CMP 공정을 이용하여 본딩 층 평탄화에 미치는 영향을 살펴보았다. CMP 공정 후 Cu dishing은 약 $180{\AA}$이었고, 웨이퍼 표면부터 Cu 범프 표면까지의 최종 높이는 약 $2000{\AA}$이었다.

• 한국진공학회지
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• 제7권2호
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• pp.88-93
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• 1998

본 연구에서는 기계-화학적 연마(Chemical-Mechanical-Polishing: CMP)공정을 이용 하여 게이트 전극을 가지는 실리콘 전계방출 소자를 제작하였으며, 또한 그 전자방출 특성 을 분석하였다. 실리콘 전계방출 소자를 제작하기 위해 실리콘을 두단계로 이루어진 건식식 각과 산화공정으로 팁을 뾰족하게 만들었으며, 게이트를 형성하기 위하여 고 선택비를 가지 는 CMP공정을 사용하였으며, 연마 시간과 연마 압력의 변화로 게이트 높이와 개구의 직경 을 쉽게 조절할 수 있었다. 또한, CMP공정시 발생되는 디싱(dishing)문제를 산화막 마스킹 을 사용함으로 해결하여 자동 정렬된 게이트전극의 개구를 깨끗하게 형성할 수 있었다. 제 작된 에미터의 높이와 팁끝의 반경은 각각 1.1$\mu$m, 100$\AA$정도이며, 제작된 2809개의 팁 어 레이로 80V의 게이트전압에서 31$\mu$A의 방출전류를 얻을 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.1600-1604
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.