• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.335-335
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• 2003

• Journal of KIISE:Information Networking
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• v.32 no.1
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• pp.29-33
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• 2005

It is not future story that host mobility in wireless network. We already have many devices which can access network among moving our locations. Internet protocol is extended to support not only host mobility but also network mobility. But nesting mobile networks and mobile hosts, there is a problem that routing path of packet becomes complex. By sequential tunneling on outgoing packet at mobile router and toward mobile network at correspondent node, it can be setting up direct path in nested mobile network environment. In this paper, we propose a method for delivering packet through optimized path by sequential tunneling. And evaluate this method by equations and simulations.

• Korean Journal of Materials Research
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• v.12 no.1
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• pp.94-99
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• 2002

The electrical properties of porous $SiO_2/ITO$ nano thin film were studied by complex impedance and conductive mechanisms were analyzed. According to the results of complex impedance, the activation energy of $SiO_2/ITO$ and $Zn-SiO_2/ITO$ were 0.309 eV, 0.077 eV in below $450^{\circ}C$ and 0.147 eV in over $450^{\circ}C$, respectively. In case of $SiO_2/ ITO$, slightly direct tunneling occurred at room temperature. The contribution for conduction was very tiny because of high barrier of silica. However, the conductivity abruptly increased in over $300^{\circ}C$ by Thermally assisted tunneling. In case of $Zn-SiO_2/ITO$, high conductivity in 1.26 ${\Omega}^{ -1}{cdot}cm^{-1}$ at room temperature appeared by space charge conduction or Frenkel-poole emission that Zn ions play a role as localized electron states.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.1-8
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• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1654-1659
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• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Bulletin of the Korean Chemical Society
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• v.25 no.4
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• pp.577-580
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• 2004

• Bulletin of the Korean Chemical Society
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• v.32 no.1
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• pp.39-40
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• 2011

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.111-111
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• 2011

Arrangement of individual atoms and molecules with atomic precision and understanding the resulting properties at the molecular level are ultimate goals of chemistry, biology, and materials science. For the past three decades, scanning probe microscopy has made strides towards these goals through the direct observation of individual atoms and molecules, enabling the discovery of new and unexpected phenomena. This talk will discuss the origin of forces governing motion of small organic molecules and their extended self-assembly into two-dimensional surface structures by direct observation of individual molecules using scanning tunneling microscopy (STM). In addition, atomic force microscopy (AFM) is utilized for the investigation of fundamental mechanisms of bone mineral dissolution by examining atomically well characterized simulated bone minerals under aqueous solution environments.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.71-72
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• 1998

반도체 집적 공정의 발달로 차세대 소자용으로 30 A 이하의 극 박막 Si02 절연막이 요구되고 있으며, 현재 제품으로 50-70 A 두께의 절연막을 사용한 것이 발표되고 있다. 절연막의 두께가 앓아질수록 많은 문제가 발생할 수 있는데 그 예로 절연막의 breakdo때둥에 의한 신뢰성 특성의 악화, 절연막올 통한 direct tunneling leakage current, boron풍의 dopant 침투로 인한 소자 특성 ( (Threshold Voltage)의 불안, 전기적 stress하에서의 leakage current증가와 c charge-trap 및 피terface s쩌.te의 생성으로 인한 소자 특성의 변화 둥으로 요약 된다. 절연막의 특성올 개선하기 위해 여러 가지 새로운 공정들이 제안되었다. 그 예로, Nitrogen올 Si/Si02 계면에 doping하여 절연막의 특성을 개선하는 방법 으로 고온 열처 리 를 NH3, N20, NO 분위 기 에서 실시 하거 나, polysilicon 또는 s silicon 기판에 nitrogen올 이온 주입하여 열처리 하는 방법, 그리고 Plasma분 위기에서 Nitrogen 함유 Gas를 이용하여 nitrogen을 doping시키는 방법 둥이 연구되고 있다. 또한 Oxide cleaning 후 상온에서 성장되는 oxide를 최소화 하여 절연막의 특성올 개선하기 위하여 LOAD-LOCK을 이용하는 방법, C뼈피ng 공정의 개선올 통한 contamination 감소와 silicon surface roughness 감소 로 oxide 신뢰성올 개선하는 방법 둥이 있다. 구조적 인 측면 에 서 는 Polysilicon 의 g없n size 를 최 적 화하여 OxideIPolysilicon 의 계면 특성올 개선하는 연구와 Isolation및 Gate ETCH공정이 절연막의 특성에 미 치 는 영 향도 많이 연구되 고 있다 .. Plasma damage 가 Oxide 에 미 치 는 효과 를 제어하는 방법과 Deuterium열처리 퉁올 이용하여 Hot electron Stress하에서 의 MOS 소자의 Si/Si02 계면의 신뢰성을 개선하고 있다. 또한 극 박막 전연막의 신뢰성 특성올 통계적 분석올 통하여 사용 가능한 수명 올 예 측 하는 방법 과 Direct Tunneling Leakage current 를 고려 한 허 용 가농 한 동작 전 압 예측 및 Stress Induced Leakage Current 둥에 관해서 도 최 근 활발 한 연구가 진행되고 있다.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.