• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.157.2-157.2
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• 2012

Direct-conversion receivers often suffer from a DC-offset that is a by-product of the direct conversion process to baseband. In general, a basic approach to reduce the DC-offset is to do simple average of the baseband signal and remove the DC by subtracting the average. However, this gives rise to a residual DC offset which degrades the performance when the receiver adopts the coding schemes with high coding rates such as 8-PSK. Therefore, more advanced methods should be additionally required for better performance. While the training sequences are basically designed to have good auto-correlation properties to facilitate the channel estimation, they may be not good for the simultaneous estimation of the channel response and the DC-offset. Also the DC offset compensation under a bad condition does not give good results due to the estimation error. Correspondingly, the proposed scheme employs the two important points. First, the training sequence codes are divided into two groups by MSE(Mean Squared Errors) for estimating the channel taps and then SNR calculated from each group is compared to predefined threshold to do fine DC-offset estimation. Next, ON/OFF module is applied for preventing performance degradation by large estimation error under severe channel conditions. The simulation results of the proposed scheme shows good performances compared to the existing algorithm. As a result, this scheme is surely applicable to the receiver design in many communications systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2391-2396
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• 2010

The power-controlled six-port element that can control the local oscillator signal power and receiving RF signal power was designed and implemented in this paper. The direct conversion six-port element configuration was proposed, which provides the constant six-port output power by controlling the six-port input power with various signal strength. The direct conversion six-port element protects the power detector element of six-port receiver from the saturation status and compensates the transmission performance degradation. For implementation of power-controlled six-port element, the power-controlled six-port element including the power controller was analyzed. The implemented power-controlled six-port element shows the power control capability of 36 dB and gain imbalance of about 1.6 dB, phase imbalance of about $4^{\circ}$ in the frequency range of 1.69 GHz. The measured results show the good performance as direct conversion front-end element.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.105-113
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• 2010

In this paper, a 1.485 Gbps video signal transmission system using the carrier frequency of 240 GHz band was designed and simulated. The sub-harmonic mixer based on Schottky barrier diode was simulated in the transmitter and receiver. Both of heterodyne and direct detection receivers were simulated for each performance analysis. The ASK modulation was used in the transmitter and the envelop detection method was used in the receiver. The transmitter simulation results showed that the RF output power was -11.4 dBm($73{\mu}W$), when the IF input power was -3 dBm(0.5 mW) at the LO power of 7 dBm(5 mW) in sub-harmonic mixer, which corresponds to SSB(Single Side Band) conversion loss of 8.4 dB. This value is similar to the conversion loss of 8.0 dB(SSB) of VDI's commercial model WR3.4SHM(220~325 GHz) at 240 GHz. The combined transmitter and receiver simulation results showed that the recovered signal waveforms were in good agreement to the transmitted 1.485 Gbps NRZ signal.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.1-7
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• 2004

The development of direct receiver techniques is expected to be a solution for future wideband or multi-band wireless systems based on software defined radio. In this Paper, we study the regeneration of I and Q signals for the SDR based direct conversion receiver, so that we can handle a wide bandwidth and maintain maximal flexibility in system utilization. After modeling the basic system considering the real wireless communication environment, and studying the impact of imperfect phase imbalance on the performance of a direct conversion receiver, we propose a suboptimal I and Q signal regeneration algorithm for the system. The proposed algerian regenerates I and Q signals using a real time early-late compensator which effectively estimates phase imbalances and gives feedback in a directreceiver. The proposed algorithm is shown to mitigate the impact of AWGN and improves performance especially at low SNR channel condition. According to the computer simulation, the BER performance of the proposed system is at least about 4 dB better than conventional systems under $45{\~}55$ degrees random phase errors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.117-123
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• 2002

This paper describes the design for the resistive FET mixer with low If for the 4-Ch DBF(Digital Beam Forming) receiver This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(If) considered in this research are 2.09 GHz, 2.08 CHz and 10 MHz, respectively. This mixer is composed of band pass filter, a low pass filter and a DC bias circuit. Super low noise HJ FET of NE3210S01 is considered in design. The RE input power, LO input power and Vcs are used -10 dBm, 6 dBm and -0.4 V, respectively. In the 4-Ch resistive FET mixer, the measured If and harmonic components of 10 MHe, 20 MHz and 2.087 CHz are about -19.2 dBm, -66 dBm and -48 dBm, respectively The If output power observed at each channel of 10 MHz is about -19.2 dBm and it is higher 28.8 dBm than the maximum harmonic component of 2.087 CHz. Each If output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.16-22
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• 1994

In this paper, transmitter and receiver modules for free space optical interconnection are implemented and characterized. In the transmitter module, bias circuitry which inject current into the direct modulated laser diode is fabricated and in the receiver module, p-i-n diode is integrated with an MMIC amplifying stage. Laser diode has a direct-modulated bandwidth of 2 GHz at 1.4 Ith bias while p-i-n diode and amplifying stage has a bandwidth of 1.3 GHz and 1.5 GHz, repectively. Optical interconnection has a bandwidth of 1.3 GHz and linearly transmit modulated voltage signal up to 1.5 Vp-p. Measured loss of optical interconnection is 5dB which is composed of optoelectronic conversion loss of 15 dB, electrical impedance mismatch loss of 6.7 dB in transmitter module and gain of 18 dB in receiver module. Seperation between transmitter and receiver can be extended up to 50 cm by using a lens.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1265-1272
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• 2006

This paper proposes a compensation method that can alleviate the problem of I/Q mismatch generated in the direct-conversion receiver of OFDM systems. In the proposed method, the amount of I/Q mismatch is estimated using null-carriers in transmitted signals, and it is subtracted from received symbols to suppress I/Q mismatch effects. Simulations show experiments that the proposed method can effectively eliminate the I/Q mismatch effects.