• 한국통신학회논문지
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• 제28권6A호
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• pp.425-432
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• 2003

본 논문에서는 직접변환방식을 이용한 CDMA 기지국용 멀티캐리어 디지털 송신기를 설계하고 시뮬레이션을 통해 그 성능을 검증해 보았다. 먼저, 멀티캐리어 송신기를 설계하기 위해 필요한 새로운 기술들을 검토해보고, 이 새로운 기술을 적용하여 멀티캐리어 송신기를 설계하고 시뮬레이션 하였다. 설계와 시뮬레이션은 Agilent Technologies사의 RF 시뮬레이션 S/W인 ADS (Advanced Design System)을 사용하였으며, 디지털 블록과 아날로그 블록으로 나누어 설계한 후 두 블록을 co-simulation하여 결과를 분석하였다. 결과에 의하면, 직접변환방식을 이용하여 멀티캐리어 디지털 송신기를 구현한 경우 최종 아날로그출력이 시스템의 요구조건 (IS-97 & 3G TS 25.104) 인 스펙트럼 마스크 특성을 만족하였다. 이것은 제안한 멀티캐리어 디지털 송신기의 성능이 CDMA 기지국에 적용될 수 있다는 것을 의미한다. 따라서, 본 논문에서 제안한 직접변환방식을 이용한 멀티캐리어 디지털 송신기는 향후 CDMA 기지국에 적용되어 구현될 때, 가격적으로나 기술적으로 한 단계 발전된 시스템을 구현할 수 있다.

• 전기전자학회논문지
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• 제13권4호
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• pp.50-56
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• 2009

본 논문은 MDDI(Mobile Display Digital Interface) 표준을 이용하여 휴대용 디지털 미디어 기기에서 사용 가능한 영상 데이터 전송 시스템을 구현하였다. 설계된 영상 데이터 전송 시스템은 QVGA급 영상을 전송하기 위해 필요한 연결선 수 6개를 사용한다. 본 논문에서는, MDDI의 영상관련 9개의 패킷을 사용하였고, 패킷프로세서는 유한상태머신 기반의 설계로 이루어졌다. Xilinx 사의 FPGA virtex4-LX60을 이용하여 제작 및 검증을 수행하였다. 설계된 영상 데이터 전송 시스템은 6개의 연결선 수로 363Mbps 데이터 전송 대역폭을 갖는다. 이는 24비트 RGB 50만 화소의 영상 데이터를 초당 30 프레임까지 전송할 수 있는 성능이다.

• 한국정보전자통신기술학회논문지
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• 제4권4호
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• pp.264-271
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• 2011

항공기의 계기착륙을 유도하는 시스템인 ILS(Instrument Landing System)는 1947년 ICAO(International Civil Aviation Organization)에서 국제표준으로 채택되어 현재는 상용시스템으로 출시되고 있다. 본 논문에서는 통합형 ILS 디지털 송수신 모듈의 설계방법을 제안하였다. 새롭게 제안한 것은 FPGA를 이용한 디지털 이중 AM 변복조기, 샘플링 클럭 생성을 위한 DDS(Direct Digital Synthesizer), DDC(Digital Down converter) 구조의 복조기, DSP 칩을 이용한 AM 스펙트럼 분석기의 디지털 설계 기법이다. 제안한 설계 방법의 유용성을 모듈 개발 및 실험을 통해 확인한 결과, 성능이 우수한 상용 시스템으로의 활용이 가능함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.415-424
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• 2016

This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.221-228
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• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.73-76
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• 2000

In tendency of digitalization, we studied about the purpose of digital modem for MRI spectrometer and advantage of digital modem compared with analog one. We introduce requirements lot designing transmitter of high speed digital modem for MRl spectrometer We also introduce its top-level and mid-level architecture. The transmitter is composed of CPC-P interface block, DUC & DAC block, RF block, master clock generation block, MCU block. Especially, DUC and its control parts are studied in detail. DUC and DAC can operate up to 52MHz and 100Msps, respectively. However we uses 35MHz as master clock and this paper shows its validity through simulations.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 춘계학술발표회논문집(1)
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• pp.471-476
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• 1996

In this study, the method to use the phase shift keying (PSK) communication technique in smart transmitter is presented. In nuclear applications. smart transmitters for various parameters are expected to improve the accuracy of measurement and to reduce the load of calibration work. The capability of communication in field level is the most important merit of the smart transmitter. The most popular method is using of digital and analog techniques simultaneously - transmitting measurements from the field at 4∼20mA while modulating the current to carry digital information in both directions over the same twisted pairs. Conventional smart transmitters use the frequency shift keying (FSK) method for digital communication. Generally, however, the FSK method has the speed limit at 1200 bps. Amount of information to transmit becomes increasing as the processing technique is improved. The PSK method is noticeable alternative for high speed digital communication, but it has non-zero DC component. In order to use the PSK method in the field transmission with smart transmitter, the method to remove the DC component is studied in this work.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.