• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.425-432
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• 2003

In this paper, we designed a multi-carrier digital transmitter for CDMA base-station using a direct conversion scheme and verified the performance through circuit simulations. We examined a new technology required to design a multi-carrier transmitter, then designed and simulated a multi-carrier digital transmitter. ADS (Advanced Design System), RF simulation S/W of Agilent Technologies, was used for designing and simulating the multi-carrier digital transmitter. First, we simulated a digital block and an analog block separately, then performed a co-simulation for entire system. From the results, the final analog outputs of the designed multi-carrier digital transmitter met the spectrum mask characteristics of IS-97 & 3G TS 25.104 standard requirements. It means that proposed scheme could be applied to implement a multi-carrier digital transmitter for CDMA base-station. Therefore, proposed multi-carrier digital transmitter using a direct conversion scheme can accomplish cost-reduction and improvements of technology in the next CDMA base-station.

• Journal of IKEEE
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• v.13 no.4
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• pp.50-56
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• 2009

This paper describes the design of image data transmitter for portable media device for Mobile Display Digital Interface standard. The transmitter uses connection lines to 6 to transmit QVGA image data. In this paper, the transmitter is using only 9 packets for image processing and a state-machine based design is adapted for packet processing. The design was verified using FPGA Xilinx virtex4-LX60. Data rate of the transmitter is 363Mbps with six connection lines. The transferring capability is 30 frame of 24bit RGB 500,000 pixel image data per second.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.264-271
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• 2011

ILS(Instrument Landing System) is the international standard system for approach and landing guidance. ILS was adopted by ICAO(International Civil Aviation Organization) in 1947 and is currently being used in commercial systems. To design the digital transmitter and receiver modules that can be mounted in the integrated ILS, we propose the digital design methods of digital double AM modulator and demodulator using FPGA chip, DDS(Direct Digital Synthesizer) for generation of sampling clock, demodulator of DDC(Digital Down Converter) structure, and spectrum analyzer using DSP chip. We demonstrate the efficiency of the proposed design method through experiments using developed transmitter and receiver modules. This system can be used as a high-performance commercial system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.415-424
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• 2016

This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.221-228
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• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.73-76
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• 2000

In tendency of digitalization, we studied about the purpose of digital modem for MRI spectrometer and advantage of digital modem compared with analog one. We introduce requirements lot designing transmitter of high speed digital modem for MRl spectrometer We also introduce its top-level and mid-level architecture. The transmitter is composed of CPC-P interface block, DUC & DAC block, RF block, master clock generation block, MCU block. Especially, DUC and its control parts are studied in detail. DUC and DAC can operate up to 52MHz and 100Msps, respectively. However we uses 35MHz as master clock and this paper shows its validity through simulations.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.05a
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• pp.471-476
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• 1996

In this study, the method to use the phase shift keying (PSK) communication technique in smart transmitter is presented. In nuclear applications. smart transmitters for various parameters are expected to improve the accuracy of measurement and to reduce the load of calibration work. The capability of communication in field level is the most important merit of the smart transmitter. The most popular method is using of digital and analog techniques simultaneously - transmitting measurements from the field at 4∼20mA while modulating the current to carry digital information in both directions over the same twisted pairs. Conventional smart transmitters use the frequency shift keying (FSK) method for digital communication. Generally, however, the FSK method has the speed limit at 1200 bps. Amount of information to transmit becomes increasing as the processing technique is improved. The PSK method is noticeable alternative for high speed digital communication, but it has non-zero DC component. In order to use the PSK method in the field transmission with smart transmitter, the method to remove the DC component is studied in this work.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.