• Proceedings of the KSR Conference
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• 2008.06a
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• pp.572-578
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• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.269-275
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• 1997

This paper presents real time digital signal processor(DSP) control of UPS system feeding processor(DSP) control of UPS system feeding nonlinear loads to provide sinusoidal inverter output voltage. The control scheme is composed of an rms voltage compensator, the load current harmonics feed-forward loop for the cancellation of output voltage harmonics, and the output voltage harmonics feedback loop for system stability. The controller employs a Texas Instruments TMS320C40GFL50 DSP.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1085-1090
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• 1995

The Discrete Cosine Transform(DCT) is effective technique for image compression, which is widely used in the area of digital signal processing. In this paper, an efficient DCT processor is proposed and simulated by using Verilog HDL. This algorithm is improved 60% in processing speed, but it's somewhat complicate compared with Y. Arai's algorithm. This algorithm will be used efficiently for real time image processing.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.9
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• pp.305-314
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• 1983

This paper presents a general purpose data acquisition system based on the microprocessor system with M 6800. instrument and lograrithmic amplifiers and A/D converters are used to implement a signal conditioner for a various kinds of signals. The proposed system has a function such that the processor may select the one of the input signals as will and also it is proved that the system may control the control signal and digital converted signal through I/O port of PIA. Practical measurement by the proposed system shows in good results.

• Journal of Biomedical Engineering Research
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• v.16 no.4
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• pp.403-414
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• 1995

It is very difficult to quantize the ECG analysis because the decision criterion for ECG is different with each other depending on the medical specialists of the heart and there are measured detecting errors for each ECG measurement system. Therefore, we developed the real-time ECG identification system using digital fuzzy processor for STD-BUS, in order to reduce ambiguity generated in the process of ECG identification and to analyze the irregular ECG stastically to ECG's repetition interval. The variables such as AGE (months), width of QRS, average RRI, and RRI were used to classify the ECG, and were applied to ECG signal indentification system which is developed for the purpose of research. It was found that the automatic diagnosis of ECG signal was possible in the real time process which was impossible in general process of algorithm.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.342-344
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• 1997

Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2196-2199
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• 2003

With the development of digital signal processor(DSP), digital pulse compressor (DPC) is commonly used in radar systems. A DPC is implemented by using finite impulse response(FIR) filter algorithm in time domain or fast Fourier transform(FFT) algorithm in frequency domain. This paper compares the computation complexity tot these two methods and calculates boundary Fm filter taps that determine which of the two methods is better based on computation amount. Also, it shows that the boundary FIR filter taps for DSP, ADSP21060, and those for computation complexity have similar characteristic.