• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2008년도 춘계학술대회 논문집
• /
• pp.572-578
• /
• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• 한국정보통신학회논문지
• /
• 제14권8호
• /
• pp.1776-1782
• /
• 2010

간섭형 Fiber optic gyroscope(FOG)는 Sagnac 효과를 이용한 회전센서로 알려져 있으며, 성능 개선을 위한 연구가 수행되어 왔다. 본 논문은 개루프 방식의 FOG 개발과 FPGA를 이용한 디지털 신호처리 기술을 다루고 있다. 첫 번째 목표는 양호한 bias stability(0.22deg/h), Scale factor stability, 단일모드 광섬유를 이용한 낮은 Angle randomwalk(0.07deg/$\sqrt[]{h}$)와 저가의 중급 자이로(Pointing grade)의 설계를 목표로 하고 있다. 두 번째 목표는 광검출기의 출력신호를 고속 ADC로 직접 변환 후 디지털 신호처리를 하는 FOG용 FPGA 개발이다. 본 연구에서 사용한 Cascaded integrator-comb(CIC)타입의 데시메이션 필터는 Adder와 Shift register만으로 구성되어 적은 계산량을 요구하므로 모든 디지털 FOG 프로세서를 저가의 프로세서로도 사용이 가능하다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1997년도 전력전자학술대회 논문집
• /
• pp.269-275
• /
• 1997

This paper presents real time digital signal processor(DSP) control of UPS system feeding processor(DSP) control of UPS system feeding nonlinear loads to provide sinusoidal inverter output voltage. The control scheme is composed of an rms voltage compensator, the load current harmonics feed-forward loop for the cancellation of output voltage harmonics, and the output voltage harmonics feedback loop for system stability. The controller employs a Texas Instruments TMS320C40GFL50 DSP.

• 전자공학회논문지B
• /
• 제32B권8호
• /
• pp.1085-1090
• /
• 1995

The Discrete Cosine Transform(DCT) is effective technique for image compression, which is widely used in the area of digital signal processing. In this paper, an efficient DCT processor is proposed and simulated by using Verilog HDL. This algorithm is improved 60% in processing speed, but it's somewhat complicate compared with Y. Arai's algorithm. This algorithm will be used efficiently for real time image processing.

• 대한전기학회논문지
• /
• 제32권9호
• /
• pp.305-314
• /
• 1983

This paper presents a general purpose data acquisition system based on the microprocessor system with M 6800. instrument and lograrithmic amplifiers and A/D converters are used to implement a signal conditioner for a various kinds of signals. The proposed system has a function such that the processor may select the one of the input signals as will and also it is proved that the system may control the control signal and digital converted signal through I/O port of PIA. Practical measurement by the proposed system shows in good results.

• 대한의용생체공학회:의공학회지
• /
• 제16권4호
• /
• pp.403-414
• /
• 1995

심전도 분석은 심장 전문의마다 기준이 다르고, 심전도 처리 시스템마다 측정된 변수 검출오차 때문에 많은 어려움이 있다. 이에 본 논문에서는 심전도 식별과정에서 발생하는 애매 모호성을 줄여주고, 불규칙한 심전도를 구간의 빈번도에 따라 통계학적으로 분석될 수 있도록 디지털 퍼지 프로세서를 사용한 STD-BUS용 실시간 심전도 신호 식별 시스템을 설계.제작하였다. 심전도를 판별하기 위해 사용된 변수는 나이, QRS폭, 평균 RRI, RRI등을 사용하였고, 이들 변수를 본 연구에서 제작한 심전도 신호 식별 시스템에 입력으로 사용한 결과, 일반 프로세서의 알고리즘에서 구별이 불가능했던 심전도 파형을 실시간으로 식별이 가능함을 확인할 수 있었다.

• 대한의용생체공학회:학술대회논문집
• /
• 대한의용생체공학회 1997년도 춘계학술대회
• /
• pp.342-344
• /
• 1997

Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

• 대한전기학회논문지:전력기술부문A
• /
• 제52권11호
• /
• pp.647-654
• /
• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• 한국방송∙미디어공학회:학술대회논문집
• /
• 한국방송공학회 2003년도 정기총회 및 학술대회
• /
• pp.69-72
• /
• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
• /
• pp.2196-2199
• /
• 2003

With the development of digital signal processor(DSP), digital pulse compressor (DPC) is commonly used in radar systems. A DPC is implemented by using finite impulse response(FIR) filter algorithm in time domain or fast Fourier transform(FFT) algorithm in frequency domain. This paper compares the computation complexity tot these two methods and calculates boundary Fm filter taps that determine which of the two methods is better based on computation amount. Also, it shows that the boundary FIR filter taps for DSP, ADSP21060, and those for computation complexity have similar characteristic.