• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.221-228
• /
• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.4
• /
• pp.745-752
• /
• 2005

In this paper we propose and implement a digital part of a receiver system for identifying a moving object and its tracking position in wireless environment. We assumed UWB(Ultra Wide Band)-based communication system for target application and used serial communication method(RS-232). The proposed digital receiver consists of RS-232-type1/RS-232-type2 for input and output of serial communication, ID Detector for detecting IDs, and PISO&Buffer circuit to buffer input signals for appropriate operation of ID Detector. We implemented the digital receiver with minimal hardware(H/W) resource according to target application of UWB-based communication system. So it correlates input patterns with pre-stored patterns though repeated detecting method for multiple IDs. Since it has reference panerns in the Ve-stored form, it can detect various IDs instantly. Also we can program content and size of reference patterns considering compatibility with other systems .The implemented H/W was mapped into XC2S100PQ208-5 FPGA of Xilinx, occupied 727($30\%$) cells, and stably operated in the clock frequency of 75MHz(13.341ns).

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.22-27
• /
• 1996

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.275-275
• /
• 2000

This paper designs a digital correlator for the integrated GPS/GLONASS receiver consisting of DCO, carrier cycle counter, code generator, code phase counter, mixer, epoch counter, accumulator. It is designed using Verilog-HDL(Verilog-Hardware Description Language) and synthesized using EDA(Electronic Design Automation) tools. The performance of the designed digital correlator is verified by the functional simulation and real satellite tracking experiments.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.2
• /
• pp.139-144
• /
• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.6
• /
• pp.17-22
• /
• 2010

In this paper, integral TS(Transport Stream) demultiplexer of a multi-modal receiver is proposed according to the multiple standards of European terrestrial digital broadcasting DVB-T(Digital Video Broadcasting Terrestrial), and mobile terrestrial digital broadcasting T-DMB(Terrestrial Digital Multimedia Broadcasting). This USB based integral receiver could recover the multi-modal broadcasting audios by memory sharing technique which was utilized to decrease the load by the control of streaming multi-modal broadcasting. As a result of performance analysis for a proposed integral TS demultiplexer, the CPU occupational efficiency of windows based integral demulitiplexing is improved compared with DVB-T, and T-DMB respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.4
• /
• pp.879-885
• /
• 2004

This paper describes an adaptive signal processing of digital receiver with digital down convertor(DDC). DDC is composed of numerically controlled oscillator(NCO) and digital low pass filler and the received signal is processed by numerical algorithm. The simulation results of digital receiver using the passband sampling technique are presented and we confirmed that the received low IF signal is converted to zero IF by numerically processed DDC. Direction of arrival(DOA) estimation technique using multiple signal classification(MUSIC) algorithm with high resolution is also discussed. We knew that an accurate resolution of DOA depends on the input sampling numbers and antenna element numbers.

• The Journal of the Acoustical Society of Korea
• /
• v.24 no.1
• /
• pp.11-20
• /
• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.49 no.11
• /
• pp.933-940
• /
• 2021

The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.803-815
• /
• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.