• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.789-796
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• 2008

This paper describes a single-phase active power filter based on a newly developed digital controller. The developed controller utilizes FFT(Fast Fourier Transform) algorithm to extract the reference signal from the load current, considering the phase-angle delay of each order of harmonics. Optimized technique was applied for whole control algorithm to implement the real-time operation of developed controller. The performance of developed controller for a single-phase active power filter was verified through computer simulations with PSCAD/EMTDC. The feasibility of hardware implementation was confirmed by building and testing a prototype. The developed digital controller for a single-phase active power filter can compensate the harmonic current generated by the power supply for digital equipment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.7
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• pp.962-967
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• 2014

In this paper, through a digital potentiometer and exponentially weighted moving average filter, pulse and PPG waveform measurable device was fabricated in radial artery. If this device is not proper about signal size in analog part, MCU can judge easily by adjusted amplification through digital potentiometer, using exponentially weighted moving average filter is able to filter out more clear value of ADC. I presumed pulse rate as value of measuring time between point of maximum contraction from sensing signal in radial artery of wrist. Therefore, this means can measure stable pulse rate and PPG waveform, finger as well as radial artery, whether signal size of each person is different finger as well as radial artery.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.758-761
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• 2007

Digital signal processing technique is applied in wide fields such as speech processing, image processing and spectrum analysis. Therefore, in order to do frequency selective operation digital filter is used in stead of analog filter and sharp filter characteristics can be implemented. Since finite impulse response (FIR) digital filter as nonrecursive type represents linear phase response characteristics and is always stable and is used in fields regarding wave information importantly such as data transmission. And due to frequency characteristics, in order to remove the Gibbs phenomenon generating around a discontinuous point, filter is designed through window function method. Therefore, in this paper to improve performance of FIR digital filter, a modified window function was applied. And the proposed method was compared with conventional methods using peak side-lobe and transition properties in simulations.

• ETRI Journal
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• v.38 no.1
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• pp.164-173
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• 2016

Demosaicing, or color filter array (CFA) interpolation, estimates missing color channels of raw mosaiced images from a CFA to reproduce full-color images. It is an essential process for single-sensor digital cameras with CFAs. In this paper, a new demosaicing method for digital cameras with Bayer-like W-RGB CFAs is proposed. To preserve the edge structure when reproducing full-color images, we propose an edge direction-adaptive method using color difference estimation between different channels, which can be applied to practical digital camera use. To evaluate the performance of the proposed method in terms of CPSNR, FSIM, and S-CIELAB color distance measures, we perform simulations on sets of mosaiced images captured by an actual prototype digital camera with a Bayer-like W-RGB CFA. The simulation results show that the proposed method demosaics better than a conventional one by approximately +22.4% CPSNR, +0.9% FSIM, and +36.7% S-CIELAB distance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.925-928
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• 2008

With basis of the development of information communication techniques in recent year, the digital processing techniquy also has been growed fast. The digital processing technique have used signals - speech and image processing- for processing of transmission and analysis. After we get and save the signals. Effective signal processing techniques have varied filters and typical digital filters are FIR filter and IIR filter. The FIR digital filter is more secure because phase response characteristics have linear phase. But, FIR digital filters have a problem to product the Gibbs phenomenon generating around a discontinuous point. A propose of filer is to remove the problem. Therefore, in this paper I was proposed a method using FIR digital filter applied a modified window function and the method was compared with conventional methods.

• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.6-8
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• 2009

In this paper. we propose receiver algorithms for VHF(Very High Frequency) digital link mode-2(VDL Mode-2) systems. Unlike conventional digital communication systems using the root raised cosine filter as a transmit and receive filter, raised cosine filter is used as a transmit filter in VDL Mode-2 systems. Hence, it is crucial to design and implement the optimum lowpass receive filter by considering the amount of inter-symbol interference and noise performance. On the other hand, due to the short preamble pattern, it is crucial to develop an efficient packet detection algorithm for reliable communication link. In this paper, we design the optimum receive filter and packet detection algorithm and evaluate the performance of receiver adopting the proposed receive filter and packet detection algorithm.