• 전기학회논문지
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• 제57권5호
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• pp.789-796
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• 2008

This paper describes a single-phase active power filter based on a newly developed digital controller. The developed controller utilizes FFT(Fast Fourier Transform) algorithm to extract the reference signal from the load current, considering the phase-angle delay of each order of harmonics. Optimized technique was applied for whole control algorithm to implement the real-time operation of developed controller. The performance of developed controller for a single-phase active power filter was verified through computer simulations with PSCAD/EMTDC. The feasibility of hardware implementation was confirmed by building and testing a prototype. The developed digital controller for a single-phase active power filter can compensate the harmonic current generated by the power supply for digital equipment.

• 한국통신학회논문지
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• 제21권1호
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• 전기학회논문지
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• 제63권7호
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• pp.962-967
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• 2014

In this paper, through a digital potentiometer and exponentially weighted moving average filter, pulse and PPG waveform measurable device was fabricated in radial artery. If this device is not proper about signal size in analog part, MCU can judge easily by adjusted amplification through digital potentiometer, using exponentially weighted moving average filter is able to filter out more clear value of ADC. I presumed pulse rate as value of measuring time between point of maximum contraction from sensing signal in radial artery of wrist. Therefore, this means can measure stable pulse rate and PPG waveform, finger as well as radial artery, whether signal size of each person is different finger as well as radial artery.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.758-761
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• 2007

디지털 신호처리 기술은 음성 및 영상 처리와 스펙트럼 분석 등과 같은 폭넓은 분야에서 활용되고 있다. 이에 따라 디지털 필터가 아날로그 필터를 대신하여 주파수 선택적 연산을 수행하기 위해 사용되고 있으며, 급준한 필터특성을 실현할 수 있다. 비재귀형으로 구성되는 FIR 디지털 필터는 항상 안정하고 선형위상응답 특성을 나타내므로, 데이터 전송과 같이 파형정보를 중요시하는 분야에 사용된다. 그리고 불연속점 부근에서 발생하는 깁스현상을 감소시키기 위해, 창함수 기법을 통해 필터를 설계한다. 따라서 본 논문에서는 FIR 필터의 성능을 향상시키기 위해, 변형된 창함수를 적용하였으며, 시뮬레이션에서 최대부엽의 크기와 천이특성을 이용하여 기존의 방법과 비교하였다.

• ETRI Journal
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• 제38권1호
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• pp.164-173
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• 2016

Demosaicing, or color filter array (CFA) interpolation, estimates missing color channels of raw mosaiced images from a CFA to reproduce full-color images. It is an essential process for single-sensor digital cameras with CFAs. In this paper, a new demosaicing method for digital cameras with Bayer-like W-RGB CFAs is proposed. To preserve the edge structure when reproducing full-color images, we propose an edge direction-adaptive method using color difference estimation between different channels, which can be applied to practical digital camera use. To evaluate the performance of the proposed method in terms of CPSNR, FSIM, and S-CIELAB color distance measures, we perform simulations on sets of mosaiced images captured by an actual prototype digital camera with a Bayer-like W-RGB CFA. The simulation results show that the proposed method demosaics better than a conventional one by approximately +22.4% CPSNR, +0.9% FSIM, and +36.7% S-CIELAB distance.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.925-928
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• 2008

현대 사회의 정보처리 기술은 디지털 기술을 기반으로 하여 빠르게 성장하고 있다. 이러한 디지털 처리기술은 신호를-음성 및 영상처리- 전달하고 해석하는 과정에서 다양한 방법을 사용하여 신호를 획득, 저장하고 있다. 효과적인 신호처리를 위해 다양한 필터가 사용되고 있으며 대표적인 디지털 필터로써는 FIR 필터와 IIR 필터가 있다. 디지털 FIR 필터는 IIR 필터에 비해 안정적이며, 선형위상 응답특성을 갖고 있다. 하지만, 디지털 FIR 필터의 불연속 구간에서의 깁스현상이 발생하는 문제점을 가지며 이것을 극복하는 것이 주요한 관건이라 하겠다. 따라서 본 논문에서는 창함수를 이용한 FIR 필터를 제시하였으며, 기존에 사용한 창함수와 비교를 통하여 성능의 우수함을 나타내었다.

• ETRI Journal
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• 제26권6호
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.6-8
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• 2009

In this paper. we propose receiver algorithms for VHF(Very High Frequency) digital link mode-2(VDL Mode-2) systems. Unlike conventional digital communication systems using the root raised cosine filter as a transmit and receive filter, raised cosine filter is used as a transmit filter in VDL Mode-2 systems. Hence, it is crucial to design and implement the optimum lowpass receive filter by considering the amount of inter-symbol interference and noise performance. On the other hand, due to the short preamble pattern, it is crucial to develop an efficient packet detection algorithm for reliable communication link. In this paper, we design the optimum receive filter and packet detection algorithm and evaluate the performance of receiver adopting the proposed receive filter and packet detection algorithm.