• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.527-536
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• 2000

This paper discusses the design of self-oscillating mixer type low noise down converter using the microwave field effect transistor. The mixer is consists of local oscillator in which high stability dielectric resonator and band pass filter to get rid of spurious oscillation at intermediate frequency stage. The microstrip antenna was integrated in the same substrate which generate 12.3GHz and low noise amplifier was also added after antenna using 3 stage of high electron mobility transistors. The output frequency from the local oscillator was chosen as 11.3GHz for the Ku-band application. The measured phase noise was -804dBc/Hz at 100kHz offset frequency, and the gain was 7～12dB in frequency range from 12.0GHz to 12.7GHz. The noise figure at intermediate frequency stage was 64H. The designed model shows less conversion loss than previous diode type mixer. The proposed mixer can be used in digital satellite broadcasting and communication system and expected to use in next generation low noise block design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.1-7
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• 2012

In this paper, a new LED driving circuit which is able to control dimming of LED is proposed using charge pump. The proposed LED driving circuit steps down the input voltage to operate LED without DC-DC converter. The operation of this driving circuit is verified by P-Spice simulation, and the characteristics of the driving circuit is measured and evaluated in the experiments. As a result, the driving circuit efficiency of 88.5[%] is obtained when all LEDs are turned on by digital control method at the highest dimming level(255/255).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.139-142
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• 2000

In this paper, we designed a Self-Oscillating mixer(SOM) for Microwave Transceiver. Implemention of SOM shows the output power of 4.33dBm at 10.750Hz and the phase-noise of -102dBc/Hz at 100KHZ offset frequency, Applying the input frequency band 11.7GHz∼12.9GHz, The designed SOM If frequency is 950MHz∼2150MHz and its conversion gain is 6dB in the If band. We convinced that SOM is applied to a digital transceiver down-converter

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1092-1099
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• 2001

본 논문에서는 무선 통신 시스템의 중간주파수 처리 단을 디지털로 신호 처리하는 DDC(Digital Down Converter)의 저전력 아키텍처를 제안한다. FIR 필터의 계산량을 줄이기 위해서 개발된 Interpolated FIR 필터가 DDC의 데시메이션 필터로 널리 사용되고 있다. 본 논문은 이와 같은 Interpolated FIR 필터의 개념이 IIR 필터에도 적용될 수 있음을 보이고, 전력 소모와 구현 면적이 기존의 Interpolated FIR 구조보다 더욱 감소된 Interpolated IIR 필터 구조를 제안하였다. CDMA IS-95 DDC 사양의 데시메이션 필터를 FIR 구조, Interpolated FIR 구조, IIR 구조, Interpolated IIR 구조로 구현하여 이 4가지 구조들의 전력소모와 구현 면적을 비교하였으며 제안된 Interpolated IIR 구조가 기존의 Interpolated FIR 구조에 비하여 15.2%의 소모전력 감소와 35.3%의 구현면적의 감소를 달성할 수 있음을 보인다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.75-76
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• 2006

A new broadcasting standard for Digital Multimedia Broadcasting(DMB) has been announced in Korea to provide audio, video, and data broadcasting services. There exist two types of DMB; terrestrial DMB and satellite DMB. And in order to service DMB on the single system, the integration of RF module is required. In this paper, we describe an integrated RF tuner module that can receive T-DMB and S-DMB at the same time, which includes an L-band down-converter, a Band III tuner, and a S-DMB tuner.

• Proceedings of the KOSOMBE Conference
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• v.1993 no.11
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• pp.190-193
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• 1993

본 연구에서는 개인용 컴퓨터(PC), 모델(MODEM), 그리고 공중회선망(PSTN)을 이용하여 다수의 환자와 병원사이에 환자 정보 및 처방정보를 주고 받을 수 있는 시스템을 구성하였다. 시스템의 구성은 환자에게서 측정된 아나로그 신호를 Analog to Digital Converter에 의해 디지탈 신호로 변환 시킨후 공증회선망을 이용하여 의사 컴퓨터에 측정된 정보를 전해주고 의사의 처방등을 다시 공중회선망을 통해 서어비스받는 형식을 취했다. 본 논문에서는 크게 두가지 점에 초점을 두었다. 첫째로 아나로그신호인 심전도 (ECG:Electrocardiogram)를 컴퓨터에서 사용가능한 화일로 생성하고, 전송해서 치사의 모니터에 본래의 파형과 비교해 왜곡이 적은, 신호로 출력해 주는데 있고, 둘째는 거의 모든 메세지를 한글화 하였고, pull down menu 구동 방식을 채택하여 컴퓨터사용에 초보적인 사람들도 쉽게 사용할 수 있게 하였다.