• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.71-76
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• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

• Journal of Power Electronics
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• v.12 no.1
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.181-182
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• 2008

In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.4
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• pp.132-137
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• 2007

The dynamic range of the radar which uses digital signal processors is limited by ADC(Analog-to-Digital Converter). That parameter and ADC loss depend on the noise level of radar receiver. In order to stabilize the performance of radar systems, it is necessary to maintain the noise level constantly. This paper presents the noise AGC(Automatic Gain Control) concept that can keep the noise level constantly and proves that the concept is acceptable through the hardware test and evaluation.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.363-366
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• 1996

A FB-ZVS(Full Bridge Zero Voltage Switching) PWM DC/DC converter for electric vehicles is simulated and implemented in this paper. The converter considered is a step-down DC/DC converter with the ratings of 312/13.5V and 1.35kW. The steady state operation of this converter is divided into six operating modes in case of continuous current mode and eight operating modes in case of discontinuous current mode. Digital simulations using PSpice are carried out to verify the steady-state analysis. A prototype converter was built in the laboratory. MOSFETs were used for swithching devices and fast recovery diodes to reduce the charge storage problem of a pn-junction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• ETRI Journal
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• v.46 no.2
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.375-383
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• 2011

This paper describes a real-time hardware simulator for a grid-tied Permanent Magnet Synchronous Generator (PMSG) wind power system, which consists of an anemometer, a data logger, a motor-generator set with vector drive, and a back-to-back power converter with a digital signal processor (DSP) controller. The anemometer measures real wind speed, and the data is sent to the data logger to calculate the turbine torque. The calculated torque is sent to the vector drive for the induction motor after it is scaled down to the rated simulator power. The motor generates the mechanical power for the PMSG, and the generated electrical power is connected to the grid through a back-to-back converter. The generator-side converter in a back-to-back converter operates in current control mode to track the maximum power point at the given wind speed. The grid-side converter operates to control the direct current link voltage and to correct the power factor. The developed simulator can be used to analyze various mechanical and electrical characteristics of a grid-tied PMSG wind power system. It can also be utilized to educate students or engineers on the operation of grid-tied PMSG wind power system.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.