• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.86-98
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• 1996

Modulation and demodualtion circuits of chaos frequency shift keying have been implemented using chua's circuits. The modulatin circuit, which is designed ot perform the frequency-doubling by coupled synchronization wihtout changing the intrinsic characteristics of its two chaos signals generated, modulates the digital input signals. The demodulation circuit detects the digital input signals form carrier by drive synchronization. these circuits, which are simplest until now and have no restriction to their digital input amplitudes, perform the aimed functions.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.95-101
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• 2016

In this paper, we introduce an implementation method of switch-based LED (Light Emitting Diode) Art logic circuits to help understanding the operation principle of digital logic circuits. Digital logic circuit practice using bread board is widely practiced in colleges or high schools in South Korea. However, actual digital logic circuit practice lacks examples of basic implementation, and as results of this problem, study with more complicated examples disturbs understanding the basic operation principle of digital logic circuits. Therefore, we proposed and tested an implementation method of switch-based LED Art logic circuits to help understanding the necessity of digital logic circuits which control signals of multiple output devices simultaneously.

• Journal of Power Electronics
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• v.17 no.3
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.59-64
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• 2008

In this paper, we developed an virtual lecture to study digital logic circuits. The contents is intended fer the students without or with little knowledge about electrics or electronics. For the beginners, the lecture contains the basic electronics and basic circuit theory as well as the degital logic circuits to be more practical lecture. And we developed the virtual circuit lab which uses real-like devices, circuits and interactive objects for the students to experience practical digital circuits. With the features described above, this contents would be useful for the beginners who want to studying digital logic circuits.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.181-184
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• 2001

This paper has been studied driving circuits in electrical valves. Also in this paper, opto-couplers of driving circuit are replaced with digital one chip of Altera company. Designs in order to realization of one chip are carried out with Altera Max Plus II. For compact size and light weight, the realization with one chip is necessary in the electrical valves. This paper has designed and presented the digital schemetic circuits, finally the driving circuits are sucessfully operated with the designed chip and showed the saving of area in the driving circuits of electric valves.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• Journal of Engineering Education Research
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• v.6 no.1
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• pp.5-14
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• 2003

This paper presents a simplified web-based simulator for digital logic circuits with which several important principles related to digital logic circuits can be understood and confirmed. The proposed simulator is implemented to have several simplified functions which are essential to the learning process of digital logic circuits. The learners by themselves simulate several digital logic circuits on the web under specific input conditions and the design/analysis of digital logic circuits can be available. The proposed simulator, combined with multimedia contents, can be used as an auxiliary educational tool and enhance the improved learning efficiency. The results of this paper can be widely used to improve the efficiency of web-based educations in the cyber space. Several simulation results are illustrated as examples to show the validity of the proposed web-based simulator.

• Journal of Sensor Science and Technology
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• v.5 no.5
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• pp.63-68
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• 1996

In order to implement the integrated capacitive pressure sensors, which contains integrated interface circuits to detect the electrical output signal, several main factors that have a bad effect on the characteristics of sensors must be improved, such as parasitic capacitance effects, temperature/thermal drift, and the leakage current of a readout circuitry. This paper describes the novel design of the dedicated CMOS readout circuitry that is consists of two capacitance to frequency converters and 4 bit digital logic compensating circuits. Dividing the oscillation frequency of a sensing sensor by that of reference sensor, this circuit is designed to eliminate the thermal/temperature drift and the effect of the leakage currents, and to access a digital signals to obtain a high signal-to-noise(S/N)ratio. Therefore, the resolution of this circuit can be increased by increasing the number of the digital bits. Digital compensated circuits of this circuits, except for the C-F converters, are fabricated on a FPGA chip, and fundamental performance of the circuits are evaluated.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.3
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• pp.27-34
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• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.