• Journal of the Computational Structural Engineering Institute of Korea
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• v.34 no.5
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• pp.301-308
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• 2021

It is important to develop a digital SOC (Social Overhead Capital) maintenance system for preemptive maintenance in response to the rapid aging of social infrastructures. Abnormal signals induced from structures can be detected quickly and optimal decisions can be made promptly using IoT sensors deployed on the structures. In this study, a digital SOC monitoring system incorporating a multimetric IoT sensor was developed for long-term monitoring, for use in cloud-computing server for automated and powerful data analysis, and for establishing databases to perform : (1) multimetric sensing, (2) long-term operation, and (3) LTE-based direct communication. The developed sensor had three axes of acceleration, and five axes of strain sensing channels for multimetric sensing, and had an event-driven power management system that activated the sensors only when vibration exceeded a predetermined limit, or the timer was triggered. The power management system could reduce power consumption, and an additional solar panel charging could enable long-term operation. Data from the sensors were transmitted to the server in real-time via low-power LTE-CAT M1 communication, which does not require an additional gateway device. Furthermore, the cloud server was developed to receive multi-variable data from the sensor, and perform a displacement fusion algorithm to obtain reference-free structural displacement for ambient structural assessment. The proposed digital SOC system was experimentally validated on a steel railroad and concrete girder bridge.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06b
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• pp.324-327
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• 2010

최근 카메라 센서는 ISP(Image Signal Processor)를 별도로 사용하지 않고 SOC(System on Chip) 방식으로 설계를 하여 소형화를 추구하고 있지만, High Resolution의 카메라가 개발 요구되어지면서 센서 Pixel 및 스위칭 트랜지스터의 집적화가 심화되고 있다. 이러한 고집적화는 카메라 센서 내 발열 관리에 대한 관심을 높여주고 있다. 본 논문에서는 우선 SOC 센서가 ISP를 탑재한 센서이므로 프로세서 발열 관리 기법에 대해 먼저 소개를 한 후, SOC 방식 센서를 대상으로 열이 발생되는 관련 조건을 확인 검사하고, 분석한 결과를 보인다. 또한 이러한 분석 결과를 토대로 발열을 제어 할 수 있는 방법으로 DAC(Digital Analog Converter)를 사용하여 센서 내 사용되는 전류 증폭을 최소화 한 설계 방식에 대해 분석해 보았으며, 전류 증폭을 최소화한 결과 최대 PCLK(Pixel Clock)에서도 열화에 따른 Noise(Hot Pixel)를 개선시킬 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of Practical Engineering Education
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• v.6 no.2
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1281-1292
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• 2014

Photovoltaic (PV) solar systems with series-connected module integrated converters (MICs) are receiving increased attention because of their ability to create high output voltage while performing local maximum power point tracking (MPPT) control for individual solar panels, which is a solution for partial shading effects in PV systems at panel level. To eliminate the partial shading effects in PV system more effectively, sub-MICs are utilized at the cell level or grouped cell level within a PV solar panel. This study presents the results of a series-output-connection MPPT (SOC-MPPT) controller for sub-MIC architecture using a single sensor at the output and a single digital MPPT controller (sub-MIC SOC-MPPT controller and architecture). The sub-MIC SOC-MPPT controller and architecture are investigated based on boost type sub-MICs. Experimental results under steady-state and transient conditions are presented to verify the performance of the controller and the effectiveness of the architecture.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.11-20
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• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Korean Journal of Heritage: History & Science
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• v.52 no.2
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• pp.4-19
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• 2019

Despite continuous volatility in ideological leanings, South Korean governments, conservative or progressive, have published a series of plans for aiding the economic development of North Korea. The Moon administration's plan is the paragon of such efforts. In addition, recent detente between the North Korean regime and the US government evokes much hope in its success. There is, hidden behind the veil of hope, apprehension about the crisis of management of cultural heritage in the North Korean region. It is believed that development policies may overwhelm efforts at conservation of cultural heritage, in particular that the hurrying of development projects would provoke insufficient and inappropriate investigation of archaeological sites., If these problems arise, responsibility for their resolution would be carried by South Korean archaeologists and governmental institutes. This paper reviews what the South Korean government has suggested for North Korea's economic recovery and examines what capability the South Korean archaeology sector has for investigating North Korean cultural heritage. It then discusses the scale of investigation needed, and what should beused as precedent in planning substantial excavations when development projects are performed in the North Korean region. Constructing a digital map system for cultural heritage of North Korea is suggested as one of the most urgent tasks precedent to substantial excavations. It is of great importance because we do not currently have any substantial information about the locations and current condition of cultural heritage sites and artifacts in the North Korean region. The mapping of Bronze Age sites in North Korea, conducted as a sort of pilot test, revealed that archaeological sites are densely distributed in several regions, especially Hwanghae-do and Pyoyang Directly-Administrated City, and that there is high potential of discovering new sites.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1840-1845
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• 2005

The SoC and digital technology development recently enabled the emergence of information devices and control devices because the SoC present many advantages such as lower power consumption, greater reliability, and lower cost. It is required to use an embedded operating system for building control systems. So far, the Real-Time operating system is widely used to implement a Real-Time system since it meets developer's requirements. However, Real-Time operating systems reveal a lack of standards, expensive development, and license costs. Embedded Linux is able to overcome these disadvantages. In this paper, the implementation of control system platform using Real-Time Embedded Linux is described. As a control system platform, we use XScale of a Soc and build Real-Time control platform using RTAI and Real-Time device driver. Finally, we address the feasibility study of the Real-Time Embedded Linux as a Real-Time operating system for mobile robots.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.789-792
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• 2011

자동차를 위한 전방향(omnidirectional) 감시 시스템, 교통 정보 수집 시스템 등 다양한 비젼 시스템에 카메라가 장착되어 사용되고 있다. 최근에는 운전자의 편의를 위하여 광각 카메라의 비선형적인 방사 왜곡을 해결하는 왜곡 보정 작업 등의 영상처리 시스템이 많이 발전하여 운전자의 사각지대를 효율적으로 최소화하고 있다. 그러나 기존의 연구에서는 카메라로부터 입력되는 왜곡 영상을 보정하는데에 별도의 H/W인 DSP(Digital Signal Processes) 또는 SOC(System On Chp) 형태의 전용 H/W를 추가하여 임베디드 시스템의 성능을 보완하고 있다. 하지만 위와 같은 별도의 H/W를 추가하여 임베디드 시스템의 성능을 보완할 경우 시스템이 복잡해지고 가격이 비싸진다는 단점이 있다. 본 논문에서는 이러한 문제점을 보완하기 위하여 왜곡 보정 알고리즘과 호모그래피(Homography) 알고리즘의 연산량을 감소시켜 임베디드 시스템 환경에서 추가의 H/W 비용없이 왜곡 보정을 수행하는 알고리즘을 제안하고, 제안한 알고리즘을 구현하여 실제 시스템에 적용한 결과를 제시하여 구현 타당성을 검증한다.