• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.126-134
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• 1996

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.

• Korean Journal of Metals and Materials
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• v.48 no.9
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• pp.856-860
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• 2010

Silver nanoparticles were formed on silica substrates through thin film dewetting at high temperature. The microstructural and morphological evolution of the particles were characterized as a function of processing variables such as initial film thickness, annealing time, and temperature. Silver thin films were deposited onto the silica using a pulsed laser deposition system and annealed in reducing atmosphere to induce agglomeration of the films. The film thicknesses before dewetting were in the range of 5 to 25 nm. A noticeable agglomeration occurs with annealing at temperatures higher than $300^{\circ}C$, and higher annealing temperature increases particle size uniformity for the same film thickness sample. Average particle size linearly correlates to the film thickness, but it does not strongly depend on annealing temperature and time, although threshold temperature for complete dewetting increases with an increase of film thickness. Lower annealing temperature develops faceted surface morphology of the silver particles by enhancing the growth of the low index crystal plane of the particles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.190-194
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• 2003

Dielectric thin films of (P $b_{0.72}$,L $a_{0.28}$) $Ti_{0.93}$ $O_3$ (PLT(28)) have been deposited on Pt(111)/Ti/ $SiO_2$/Si(100) substrates in-situ by pulsed laser deposition using different annealing and deposition Processes. We have investigated the effect of hydrogen annealing on the ferroelectric properties of PLT thin films and found that the annealing process causes the diffusion of hydrogen into the ferroelectric film resulting in the destruction of polarization. We have tried to form the film by a two-step deposition process In order to improve electrical property. Two-step process to grow PLT films was adopted and verified to be useful to enlarge the grain size of the film and to reduce the leakage current characteristics. Structural properties and electrical properties including dielectric constant, ferroelectric characteristics, and leakage current of PLT thin films were shown to be strongly influenced by grain size. The film deposited by using two-step Process including pre-annealing treatment has a strongly(111) orientation. However, the films deposited by using single -step process with hydrogen annealing process show the smallest grain size. The film deposited by using two-step process including pre-annealing treatment shows the leakage current density of below 10$^{-7}$ A/c $m^2$ for the field of smaller than 100 kV/cm. However, the films deposited by using single-step process with hydrogen annealing process and pre-annealing process show worse leakage current density than the film deposited by using two-step process including pre-annealing treatment.tment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.66-66
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• 2008

Most of the properties of ITO films depend on their substrate nature, deposition techniques and ITO film composition. For the display panel application, it is normally deposited on the glass substrate which has high strain point (>575 degree) and must be deposited at a temperature higher than $250^{\circ}C$ and then annealed at a temperature higher than $300^{\circ}C$ in order to high optical transmittance in the visible region, low reactivity and chemical duration. But the high strain point glass (HSPG) used as FPDs is blocking popularization of large sizes FPDs because it is more expensive than a soda lime glass (SLG). If the SLG could be used as substrate for FPDs, then diffusion of Na ion from the substrate occurs into the ITO films during annealing or heat treatment on manufacturing process and it affects the properties. Therefore proper care should be followed to minimize Na ion diffusion. In this study, we investigate the electrical, optical and structural properties of ITO films deposited on the SLG and the Asahi glass(PD200) substrate by rf magnetron sputtering using a ceramic target ($In_2O_3:SnO_2$, 90:10wt.%). These films were annealed in $N_2$ and air atmosphere at $400^{\circ}C$ for 20min, 1hr, and 2hrs. ITO films deposited on the SLG show a high electrical resistivity and structural defect as compared with those deposited on the PD200 due to the Na ion from the SLG on diffuse to the ITO film by annealing. However these properties can be improved by introducing a barrier layer of $SiO_2$ or $Al_2O_3$ between ITO film and the SLG substrate. The characteristics of films were examined by the 4-point probe, FE-SEM, UV-VIS spectrometer, and X-ray diffraction. SIMS analysis confirmed that barrier layer inhibited Na ion diffusion from the SLG.

• Nuclear Engineering and Technology
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• v.43 no.2
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• pp.159-166
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• 2011

Si-rich-layer-coated U-7 wt%Mo plates were prepared in order to evaluate the diffusion barrier performance of the Si-rich layer in U-Mo vs. Al interdiffusion. Pure Si powder was used for coating the U-Mo plates by annealing at $900^{\circ}C$ for 1 h under vacuum of approximately 1 Pa. Si-rich layers containing more than 60 at% of Si were formed on U-7 wt%Mo plates. Diffusion couple tests were conducted in a muffle furnace at $560-600^{\circ}C$ under vacuum using Si-rich-layer-coated U-Mo plates and pure Al plates. Diffusion couple tests using uncoated U-Mo plates and Al-(0, 2 or 5 wt%)Si plates were also conducted for comparison. Si-rich-layer coatings were more effective in suppressing the interaction during diffusion couple tests between coated U-Mo plate and Al, when compared with U-Mo vs. Al-Si diffusion couples, since only small amounts of Al in the coating could be found after the diffusion couple tests. Si-rich-layer-coated U-7wt%Mo particles were also prepared using the same technique for U-7 wt%Mo plates to observe the microsturctures of the coated particles.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.2
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• pp.55-58
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• 2003

This paper examines the electrical characteristic of single oxide layer due to various diffusion conditions, substrate orientations, substrate resistivity and gas atmosphere in a diffusion furnace. The oxide quality was examined through the capacitance-voltage characteristic due to the annealing time after oxidation process, and the capacitance-voltage characteristics of the single oxide layer by will be described via semiconductor device simulation.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.49-55
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• 2016

The effects of post-annealing and temperature/humidity conditions on the interfacial adhesion energies of atomic layer deposited RuAlO diffusion barrier layer for Cu interconnects were systematically investigated. The initial interfacial adhesion energy measured by four-point bending test was $7.60J/m^2$. The interfacial adhesion energy decreased to $5.65J/m^2$ after 500 hrs at $85^{\circ}C$/85% T/H condition, while it increased to $24.05J/m^2$ after annealing at $200^{\circ}C$ for 500 hrs. The X-ray photoemission spectroscopy (XPS) analysis showed that delaminated interface was RuAlO/$SiO_2$ for as-bonded and T/H conditions, while it was Cu/RuAlO for post-annealing condition. XPS O1s peak separation results revealed that the effective generation of strong Al-O-Si bonds between $AlO_x$ and $SiO_2$ interface at optimum post-annealing conditions is responsible for enhanced interfacial adhesion energies between RuAlO/$SiO_2$ interface, which would lead to good electrical and mechanical reliabilities of atomic layer deposited RuAlO diffusion barrier for advanced Cu interconnects.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.87-91
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• 2004

We have investigated the effects of W-N/Pt bottom electrode on the ferroelectric degradation of $Sr_{0.8}Bi_{2.4}Ta_2O_9(SBT)/Pt$ due to hydrogen annealing at $350^{\circ}C$ in $N_2$ gas atmosphere containing $5{\%}\;H_2$ gas for 1hr. As a result, inserting the W-N thin films between SBT and Pt, this W-N thin film prevents hydrogen molecules to be chemisorbed at the Pt electrode surface of at the electrode/ferroelectric interface during hydrogen annealing. These hydrogen atoms can diffuse into the SBT and react with the oxide causing the oxygen deficiency in the SBT film, which will result in the ferroelectric degradation. Experimental results show that W-N thin film is a good diffusion barrier during the hydrogen annealing.