• 한국재료학회지
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• 제14권12호
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• pp.829-834
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• 2004

Annealing of $Cu(B)/Ti/SiO_2$ in vacuum has been carried out to investigate the effects of Ti underlayer on microstructure in $Cu(B)/Ti/SiO_2$ structures. For comparison, $Cu(B)/Ti/SiO_2$ structures was also annealed in vacuum. Three different temperature dependence of Cu growth can be seen in $Cu(B)/Ti/SiO_2$; B precipitates- pinned grain growth, abnormal grain growth, normal grain growth. The Ti underlayer having a strong affinity for B atoms reacts with the out-diffused B to the Ti surface and forms titanium boride at the Cu-Ti interface. The formation of titanium boride acts as a sink for the out-diffusion of B atoms. The depletion of boron in grain boundaries of Cu films, as results of the rapid diffusion of B along the grain boundaries and the insufficient segregation of B to the grain boundaries, induces grain boundaries to migrate and causes the abnormal grain growth. The increased bulk diffusion coefficient of B within Cu grains can be responsible for the normal grain growth occurring in the annealed $Cu(B)/Ti/SiO_2\;at\;600^{\circ}C$. In contrast, the $Cu/SiO_2$ structures show only the abnormal growth of grains and their sizes increasing as the temperature increases above $400^{\circ}C$.

• 한국분말재료학회지
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• 제22권6호
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• pp.432-437
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• 2015

The en-riched $^{58}Ni$ powders are dissolved in acid solution and coated on a Cu target for proton irradiation at cyclotron to produce $^{57}Co$ radioisotope. The condition of the plating bath and the coating process are determined using the en-riched powders. To establish the coating conditions for $^{57}Co$, non-radioactive Co ions are dissolved in an acid solution and electroplated on to a rhodium plate. The thermal diffusion of electroplated Co into a rhodium matrix was studied to apply a $^{57}Co$ Mssbauer source. The diffusion depth from surface to matrix of Co is depended on the annealing temperature and time. The deposited Co atoms diffuse completely into a rhodium (Rh) matrix without substantial loss at an annealing temperature of 1200 for 4 hours.

• 한국전기전자재료학회논문지
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• 제12권1호
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• pp.35-43
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• 1999

Microstructures and dielectric properties of (Sr$\_$1-x/Ca$\_$x/) TiO$_3$-0.006Nb$_2$O$\_$5/ (0.05$\leq$x$\leq$0.2) boundary layer ceramics were investigated. The samples fired in a reducing atmosphere(N$_2$) were painted on the surface with CuO paste for the subsequent grain boundary diffusion, and then annealed at 1100$^{\circ}C$ for 2 hrs. The metal oxide of CuO infiltrated by thermal diffusion from surface of sample presents continuously in not grain but only grain boundary, and makes up thin boundary phase. The SEM photo, and EDAX revealed that CuO was penetrated rapidly into the bulk along the grain boundaries during the annealing. The average grain sizes is continuously increased as the content of substitutional Ca is increased from 5[mol%] to 15[mol%], but the average grain size of the sample with content of 20[mol%] Ca is slightly decreased. In the samples with content of 10∼15[mol%] Ca, excellent dielectric properties were obtained as follows; dielectric constant <25000, dielectric loss <0.3[%], and capacitance change rate as a function of temperature <${\pm}$10[%], respectively. All samples in this study exhibited dielectric relaxation with frequency as a functior of the temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.709-712
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• 2001

The effects of post annealing temperature by the Rapid Thermal Annealing(RTA) on the electrical properties of Pb(Zr,Ti)O$_3$(PZT) thin film were investigated. Analyses by the RTA treatments reveled that the leakage current of PZT thin films strongly depend on heating temperature and time. It was found that leakage current properties of PZT capacitor were changed by heating temperature during the RTA annealing. On Pt/Ti/Si substrates, PZT films are deposited at 350 $^{\circ}C$ by rf magnetron sputtering. The X-ray diffusion (XRD) was confirmed the formation of PZT thin film. Leakage current characteristics were improved with decreasing the post annealing temperature of PZT thin film. RTA annealed film on the 700$^{\circ}C$ shows ferroelectric and electrical properties with a remanent polarization of 12.4${\mu}$C/$\textrm{cm}^2$ coercive field of 117kV/cm, leakage current J= 6.2${\times}$10$\^$-6/ A/$\textrm{cm}^2$

• 한국전기전자재료학회논문지
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• 제13권6호
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• pp.467-471
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• 2000

The thermal annealing effect of $Zn_{0.9}Cd_{0.1}$ single quantum-well structures grown by molecular beam epitaxy is investigated. As the results of before and after rapid thermal annealed samples a red shift of E1-HH1 peak by Cd interdiffusion during thermal annealing of ZnCeSe/ZnSe sample was observed. In the case of annealed sample over $450^{\circ}C$ donor and acceptor impurities related peaks were observed which seems to be due to a diffusion of Ga and As from GaAs substrate. And also interdiffusion phenomena is idenified by the results of DCX measurements and which are consisten with the PL measurements.

• 한국전기전자재료학회논문지
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• 제19권1호
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• pp.52-57
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• 2006

Precision thin film resistors using evanohm R alloy were fabricated by do magnetron sputtering method. The physical and electrical properties of the resistors were studied after treatment of thermal annealing. The crystallization of the film was increased as the annealing temperature increase. Diffusion and oxidation of Cr and Al elements were occurred into the film surface. The minimum TCR values of 10.46 ppm/$^{\circ}C$ and 10.65 ppm/$^{\circ}C$ were measured at the annealing temperatures of $200^{\circ}C$ and $300^{\circ}C$, respectively. We are conducting additional studies to improve characteristics of our resistors for practical device application.

• 한국재료학회지
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• 제34권2호
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• pp.79-84
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• 2024

Thin films of yttria-stabilized zirconia (YSZ) nanoparticles were prepared using a low-temperature deposition and crystallization process involving successive ionic layer adsorption and reaction (SILAR) or SILAR-Air spray Plus (SILAR-A+) methods, coupled with hydrothermal (175 ℃) and furnace (500 ℃) post-annealing. The annealed YSZ films resulted in crystalline products, and their phases of monoclinic, tetragonal, and cubic were categorized through X-ray diffraction analysis. The morphologies of the as-prepared films, fabricated by SILAR and SILAR-A+ processes, including hydrothermal dehydration and annealing, were characterized by the degree of surface cracking using scanning electron microscopy images. Additionally, the thicknesses of the YSZ thin films were compared by removing diffusion layers such as spectator anions and water accumulated during the air spray plus process. Crack-free YSZ thin films were successfully fabricated on glass substrates using the SILAR-A+ method, followed by hydrothermal and furnace annealing, making them suitable for application in solid oxide fuel cells.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• 대한전자공학회논문지
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• 제20권1호
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• pp.22-26
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• 1983

열확산(thermal diffusion)법을 이용하여 면적이 3.36㎠인 P+N 전지와 P+NN+ 전지를 제작하였다. 100mW/㎠의 인공 조명에서 측정한 결과 940℃에서 15분 보론확산(boron Predeposition)을 하고, 800℃에서 20분 열처리(annealing)하여 제작한 P+N전지는 전면적(수광면적) 변환 효율이 13.4%(14.7%)이었다. 뒷면을 1050℃에서 인(Phosphorus)을 확산한 후, 앞면을 940℃에서 15분 보론 확산하고, 800℃에서 50분 열처리하여 만든 P+NN+전지의 전면적(수광면적) 변환 효율은 14.3%(15.6%)이었다. 뒷면의 인 확산으로 게더링(gettering) 작용과 BSF 효과에 의해서 P+NN+ 전지가 P+N전지보다 캐리어 수명이 약 2∼3배 증가되었다. 그리고 효율 개선을 위해 AR로팅, Ag전기도금, 미세한 그리드 패턴, 앞면 불순물 주입량 조절 등을 행하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.