• 월간포장계
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• 통권247호
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• pp.53-73
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• 2013

한국건설생활환경시험연구원은 2012년 2월 15일부터 11월 30일까지 식품의약품안전청에서 시행한 용역연구개발과제의 일환으로 '의료기기 포장 밸리데이션 적용 방안'을 연구했다. 본 고에서는 연구 보고서 내용 중 일부를 소개하도록 한다.

• 마이크로전자및패키징학회지
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• 제10권4호
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• pp.65-71
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• 2003

압전 세라믹스를 이용하여 약품 분사용 초음파분사 노즐을 제작하였다. 정수장의 혼화 공정에 사용되는 약품(응집제)의 고효율 분산을 위해 분사 노즐을 설계하였으며 압전세라믹을 최적화하였다. 제작된 초음파 약품 분사 노즐을 패키징하여 정수장의 약품 혼화 과정에 적용하여 약품사용의 고 효율화와 사용량 저감을 위한 연구를 진행하였다. 압전체는 실리콘으로 마감처리를 하였으며 Al으로 패키징하였다. 본 초음파 분사 노즐 시스템을 적용하여 혼화지에 실험한 결과 약품의 순간 혼화를 촉진시키는 기술로 투입 약품량을 저감시킬 수 있을 것으로 판단된다. 초음파 발진 약품 분사시, 무발진과 비교하여 대장균 제거 효율에서 현저하게 높아졌다.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.13-18
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• 2012

By the need for high-speed data transmission in PCB, the studies on the optical PCB has been conducted with optical interconnection and its packaging technology. Particularly, the polymer-based optical interconnection has been extensively studied with the advantages such as cost-effective and ease of process. For high-efficiency and passive alignment, the studies were performed using the 45 degree mirrors, MT connector, and etc. In this work, integrated PLC device and fiber alignment array block was fabricated by using imprint technology to solve the alignment and array problem of optical device and the optical fiber. The fabricated integrated block for optical interconnection of PLC device has achieved higher precision of decreasing the dimensional error of the patterns by optimization of process and its insertion loss has an average value of 4.03dB, lower than criteria specified by international standard. In addition, a optical waveguide with built-in lens has been proposed for high-efficiency and passive alignment. By simulation, it was confirmed that the proposed structure has higher coupling efficiency than conventional no-lens structure and has the broad tolerance for the spatial offset of optical waveguide.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.27-33
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• 2010

We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.

• ETRI Journal
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• 제41권6호
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• pp.820-828
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• 2019

A highly reliable conductive adhesive obtained by transient liquid-phase sintering (TLPS) technologies is studied for use in high-power device packaging. TLPS involves the low-temperature reaction of a low-melting metal or alloy with a high-melting metal or alloy to form a reacted metal matrix. For a TLPS material (consisting of Ag-coated Cu, a Sn96.5-Ag3.0-Cu0.5 solder, and a volatile fluxing resin) used herein, the melting temperature of the metal matrix exceeds the bonding temperature. After bonding of the TLPS material, a unique melting peak of TLPS is observed at 356 ℃, consistent with the transient behavior of Ag₃Sn + Cu₆Sn₅ → liquid + Cu₃Sn reported by the National Institute of Standards and Technology. The TLPS material shows superior thermal conductivity as compared with other commercially available Ag pastes under the same specimen preparation conditions. In conclusion, the TLPS material can be a promising candidate for a highly reliable conductive adhesive in power device packaging because remelting of the SAC305 solder, which is widely used in conventional power modules, is not observed.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.25-29
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• 2002

기존 홀 센서의 단점을 개선하기 위해서 트랜치를 이용한 수직 홀 센서를 제작하였다. 수직 홀 센서는 센서의 칩 표면에 수평 자계를 검출할 수 있으며, 홀 센서는 실리콘 직접 본딩 기술에 의해 제작된 SOI 기판 위에 제작하였다. 기판 아래의 $SiO_2$층과 마이크로머시닝에 의한 트랜치가 홀 센서의 동작 영역을 정의한다. 홀 센서의 감도는 150V/AT로 측정되었으며 안정된 값을 나타내었다.

• 한국기계가공학회지
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• 제19권2호
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• pp.63-68
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• 2020

In this study, we analyzed a cold draw (CD) bar packaging automation facility to examine its structural safety. The structural analysis focused on the frame part of the automatic packing machine for the CD round rod widely used in the industrial field, as well as the package supply device, banding suit, and crane part. As a result, we concluded that the structural safety for the banding suit, crane, and package supply device have been secured (safety factors of 9.8, 7.5, and 14.5, respectively). In addition, the safety factor of the transfer was 4.0.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.129-133
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• 2001

In this paper, hermetic sealing was studied fur wafer level packaging of the MEMS devices. With the flip-chip bonding method, this B-stage epoxy sealing will be profit to MEMS device sealing and further more RF-MEMS device sealing. B-stage epoxy can be cured 2-step and hermetic sealing can be obtained. After defining $500{\mu}{\textrm}{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was then aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line were maintained during the sealing process. The height of the seal-line was controlled within $\pm0.6${\mu}{\textrm}{m}$ and the strength was measured to about 20MPa by pull test. The leak rate of the epoxy was about $10^7$ cc/sec from the leak test.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.39-47
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• 2002

Heat is always the root of stress acting upon the electronic package, regardless of the heat due to the device itself during operation or working under the adverse environment. Due to the significant mismatch in coefficient of thermal expansion (CTE) and the thermal conductivity (K) of the packaging components, on one hand intensive research has been conducted in order to enhance the device reliability by minimizing the mechanical stressing and deformation within the package. On the other hand the effectiveness of different thermal enhancements are pursued to dissipate the heat to avoid the overheating of the device. However, the interactions between the thermal-mechanical loading has not yet been address fully. in articular when the temperature gradient is considered within the package. To address the interactions between the thermal loading upon the mechanical stressing condition. coupled-field analysis is performed to account the interaction between the thermal and mechanical stress distribution. Furthermore, process induced defects are also incorporated into the analysis to determine the effects on thermal conducting path as well as the mechanical stress distribution. It is concluded that it feasible to consider the thermal gradient within the package accompanied with the mechanical analysis, and the subsequent effects of the inherent defects on the overall structural integrity of the package are discussed.