• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• 대한전기학회논문지
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• 제43권7호
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• pp.1121-1127
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• 1994

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• 한국전기전자재료학회논문지
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• 제15권5호
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• pp.398-405
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• 2002

The degradation characteristics of MgO additive for the ZnO ceramic devices fabricated by the standard ceramic techniques are investigated in this study. These devices were made from basic Matsuoka's composition. Especially, MgO was added to analyze the degradation characteristics and devices were sintered in air at $1200^{\circ}C$. The conditions of DC degradation test were $115\pm2^{\circ}C$ for 12h. Using XRD and SEM, the phase and microstructure of samples were analyzed, respectively. The elemental analysis in the microstructures was performed by EDS, E-J analysis was used to determine $\alpha$. Frequency analysis was accomplished to understand the relationship between $R_G$ and $R_B$ with the electric stress at the equivalent circuit.

• 한국전자통신학회논문지
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• 제8권1호
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• pp.55-64
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• 2013

본 논문에서는 UWB 기술 기반 무선 USB(WUSB) 프로토콜에서, 디바이스들의 이동성으로 인해 발생하는 Private Distributed Reservation Protocol (DRP) 예약 충돌 현상을 분석한다. 그리고 Private DRP 예약 충돌시 발생하는 성능 저하를 감소시키기 위해 Private DRP 릴레이 통신 기술을 제안한다. 본 논문에서 제안하는 Private DRP 릴레이 통신 프로토콜은 충돌대상 디바이스에게 예약된 자원을 유지할 수 있도록 Direct Link 뿐만 아니라, Private DRP 예약 충돌 시 릴레이 노드를 경유하여 또 다른 Indirect Link 링크를 빠르게 예약할 수 있는 분산적인 자원 예약 프로토콜을 제안한다.

• 한국통신학회논문지
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• 제39C권8호
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• pp.696-707
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• 2014

본 논문에서는 UWB 기술 기반 무선 USB(WUSB) 프로토콜에서, 디바이스들의 이동성으로 인해 발생하는 Private Distributed Reservation Protocol (DRP) 예약 충돌 현상을 분석한다. 그리고 Private DRP 예약 충돌 시 발생하는 성능 저하를 감소시키기 위해 Private DRP 릴레이 통신 기술을 제안한다. 본 논문에서 제안하는 Private DRP 릴레이 통신 프로토콜은 충돌대상 디바이스에게 예약된 자원을 유지할 수 있도록 Direct Link 뿐만 아니라, Private DRP 예약 충돌 시 릴레이 노드를 경유하여 또 다른 Indirect Link 링크를 빠르게 예약할 수 있는 분산적인 자원 예약 프로토콜을 제안한다.

• 정보저장시스템학회논문집
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• 제11권2호
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• pp.31-35
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• 2015

The Blu-ray Disc Recordable-Triple Layer (BD-R TL) media is considered as one of strong candidates for archival application among optical media formats, due to its large capacity. However, the long-term stability and degradation aspect have not been fully understood yet for BD-R TL media. Thus, the BD-R TL media were recorded at full tracks and analyzed by the random-symbol error rate (R-SER) measurement at different recording layers and recording positions after the accelerated aging test to understand its long-term stability. Finally, the general degradation aspect of BD-R TL media was discussed to improve the long-term stability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• 한국전기전자재료학회논문지
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• 제27권12호
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.