• Title/Summary/Keyword: device capacitance

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Fabrication of planar type GaInAs PIN photodiode and its characteristics (평면형 GaInAs/InP PIN Photodiode 제작 및 특성)

  • 박찬용
    • Proceedings of the Optical Society of Korea Conference
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    • 1991.06a
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    • pp.135-138
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    • 1991
  • A planar type PIN photodiode has been fabricated and discussed. We used OMVPE systems to grow the structure of u-InP/u-InP/n-InP. P-n junction was formed by Zn-diffusion method at 50$0^{\circ}C$, for 5 minitues. The device characteristics at 5V were as follows: Dark currents were distributed around 1nA. Capacitance was 1.6pF and responsivity was above 0.85 mA/mW for 1.3${\mu}{\textrm}{m}$ wavelength. Measured cut-off frequency(-3dB) at -5V was 1.1㎓.

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Dynamic Response of Organic Right-emitting Diodes in ITO/Alq3 Structure

  • Lee, Dong-Gyu;Lee, Joon-Ung
    • Transactions on Electrical and Electronic Materials
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    • v.6 no.3
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    • pp.97-100
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    • 2005
  • Dynamic response of organic light-emitting diodes were analyzed in $ITO/Alq_3$(100 nm)/Al device structure with a variation of voltage an frequency. At low frequency region, complex impedance is mostly governed by resistive component, and at high frequency region by capacitive component. Also, we have evaluated resistance, capacitance and permittivity of devices.

Optically Controlled Silicon MESFET Modeling Considering Diffusion Process

  • Chattopadhyay, S.N.;Motoyama, N.;Rudra, A.;Sharma, A.;Sriram, S.;Overton, C.B.;Pandey, P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.3
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    • pp.196-208
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    • 2007
  • An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

Organic Thin Film Transistors with Gate Dielectrics of Plasma Polymerized Styrene and Vinyl Acetate Thin Films

  • Lim, Jae-Sung;Shin, Paik-Kyun;Lee, Boong-Joo
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.2
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    • pp.95-98
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    • 2015
  • Organic polymer dielectric thin films of styrene and vinyl acetate were prepared by the plasma polymerization deposition technique and applied for the fabrication of an organic thin film transistor device. The structural properties of the plasma polymerized thin films were characterized by Fourier-transform infrared spectroscopy, X-ray diffraction, atomic force microscopy, and contact angle measurement. Investigation of the electrical properties of the plasma polymerized thin films was carried out by capacitance-voltage and current-voltage measurements. The organic thin film transistor device with gate dielectric of the plasma polymerized thin film revealed a low operation voltage of −10V and a low threshold voltage of −3V. It was confirmed that plasma polymerized thin films of styrene and vinyl acetate could be applied to functional organic thin film transistor devices as the gate dielectric.

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

  • Lyu, Jong-Son
    • ETRI Journal
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    • v.15 no.2
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    • pp.11-25
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    • 1993
  • Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

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A Study on the Dielectric Property Organic Ultra Thin film (유기초박막의 유전특성에 관한 연구)

  • Kim, Dong-Kwan;Song, Jin-Won;Lee, Kyung-Sup
    • Proceedings of the KIEE Conference
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    • 2001.11a
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    • pp.87-89
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    • 2001
  • The structure of manufactured device is Cr-Au/Arachidic acid/Al, the number of accumulated layers are 13, 17 and 19. The I-V characteristic of the device is measured from -2[V] to +2[V] and the characteristic of current-time of the devices. We have investigated the capacitance because this fatty acid system have a accumulated layers. The maximum value of measured current is increased as the number of accumulated layers are decreased. The capacitor properties of a thin film is better as the distance between electrodes is smaller. The results have shown the insulating materials and could control the conductivity by accumulated layers.

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Electrical properties of $SiO_2$/InSb prepared by low temperature remote PECVD (Remote PECVD로 저온성장된 $SiO_2$/InSb의 전기적 특성)

  • 이재곤;박상준;최시영
    • Journal of the Korean Vacuum Society
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    • v.5 no.3
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    • pp.223-228
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    • 1996
  • $SiO_2$ insulator layers on InSb have been prepared by remote PECVD system a low temperature below $200^{\circ}C$. The effects of deposition pressure, temperature, and gas flow ratio on the physical and electrical characteristics of the $SiO_2$ were studied. The InSb MIS device using $SiO_2$ was fabricated and measured its current-voltage and capacitance-voltage characteritance-voltage charateristics at 77K. The films evaluated Auger electron spectroscopy showed that composition atoms were distributed uniformaly throughout the oxide film and the outdiffusion of substrate atoms into the oxide were few. The leakage current density of the MIS device was about 6.26nA/$\textrm{cm}^2$ at 0.75MV/cm , and the breakdown voltage was about 1MV/cm. The interface-stage density at mid-bandgap extracted from 1MHz C-V measurement was $54\times 10^{11}\textrm{cm}^2-2V^{-1}$.

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BUCK DC-DC Converter to Reduce Power Stress of Switching Device (스위칭 소자의 전력 스트레스를 제거하기 위한 BUCK DC-DC 컨버터)

  • 이성백;박진홍
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.10 no.6
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    • pp.54-61
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    • 1996
  • In this paper, the conventional ZVS-QRC buck dc-dc converter is analyzed using simulation and the problem in confirmed through it. According to varying the load resistance lower, it is provided that the stress of the device is increased. The reason is seen that the voltage is increased by parasitic capacitance of freewheeling diode. Novel ZVS-converter is proposed to improve the problems.

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Single Stage Resonant Power Supply for Driving Magnetron Device (마그네트론 구동용 단일단 공진형 전원장치)

  • Jeong Jin-Beom;Yeon Jae-Eul;Kim Hee-Jun
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.53 no.10
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    • pp.625-633
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    • 2004
  • This paper proposed a boost input type single stage resonant power supply for driving magnetron device. The proposed power supply can control both input power factor and output power at the same time. Also, because ZVS is achieved using the resonance between leakage inductance and resonant capacitance, switching losses are drastically reduced. To prevent breakdown or moding phenomenon of the magnetron due to excessive starting voltage, variable frequency ignition method is also proposed. Experimental results for the prototype power supply are presented and discussed to verify the validity of the proposed power supply.

A New Structure of SOI MOSFETs Using Trench Mrthod (트랜치 기법을 이용한 SOI MOSFET의 전기적인 특성에 관한 연구)

  • Park, Yun-Sik;Sung, Man-Young;Kang, Ey-Goo
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 2003.11a
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    • pp.67-70
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    • 2003
  • In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

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