• Transactions of the Korean Society for Noise and Vibration Engineering
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• 제18권12호
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• pp.1262-1269
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• 2008

Though multilayered foam-panel structures have been widely used to reduce sound transmission in various fields, most of the previous works to design them were conducted by repeated analyses or experiments based on initially given configurations or sequences. Therefore, it was difficult to obtain an optimal sequence of multilayered foam-panel structure yielding superior sound isolation capability. In this work, we propose a new design method to sequence a multi-panel structure lined with a poroelastic material having maximized sound transmission loss. Being formulated as a one-dimensional topology optimization problem fur a given target frequency, the optimal sequencing of panel-poroelastic layers is systematically carried out in an iterative manner. In this method, a panel layer is expressed as a limiting case of a poroelastic layer to facilitate the optimization process. This means that main material properties of a poroelastic material are treated as interpolated functions of design variable. The designed sequences of panel-poroelastic multilayer were shown to be significantly affected by the target frequencies; more panels were obtained at higher target frequency. The sound transmission loss of the system was calculated by the transfer matrix derived from Biot's theory.

• IE interfaces
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• 제14권3호
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• pp.247-254
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• 2001

As current postal automation is limited to dispatch and arrival sorting, delivery sequence sorting is performed manually by each postman. It not only acts as a bottleneck process in the overall mailing process but is expensive operation. To cope with this problem effectively, delivery sequence sorting automation is required. The important components of delivery sequence sorting automation system are sequence sorter and Hangul OCR which function is to extract the address of delivery point. DSI database will be interfaced to both Hangul OCR and sequence sorter for finding the accurate delivery sequence number and stacker number. The objectives of this research are to develop DSI(Delivery Sequence Information) database prototype and client application for managing information effectively. For database requirements collection and analysis, we draw all possible sorting plans, and apply the AHP(Analytic Hierarchy Process) method to determine the optimal one. And then, we design DSI database schema based on the optimal one and implement it using Oracle RDBMS. In addition, as address information in DIS database consist of hierarchical structure which has its correspondence sequence number, so it is important to reorganize sequence information accurately when address information is inserted, deleted or updated. To increase delivery accuracy, we reflect this point in writing application.

• Journal of Korean Society of Transportation
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• 제20권7호
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• pp.23-29
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• 2002

Five and more leg intersections have been still in operation in many urban areas. The number of conflicts in five leg intersection is more than four leg intersection. The signal timing design in the five leg intersection should be performed not only to reduce delay but also to increase safety. This paper suggests safety enhanced signal phase sequence design of a rotary with five leg intersection such as phase sequence minimizing the number of conflict points at the rotary with five leg intersections and the phase-length-design procedure by utilizing the Traffic Network Study Tool(TRANSYT). Field data was collected from Gonguptap five leg intersection in Ulsan and TRANSYT-7F was applied for signal timing design model. Optimal signal phase length and sequence of TRANSYT-7F is rearranged based on the Principal of "two moving traffic flows per phase". In conclusion, proposed signal phase design increased delay by 6.2% compared with the optimal signal phase of TRANSYT-7F. However, it could decrease the number of conflict in the five leg intersection by 61.5%.

• International Journal of High-Rise Buildings
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• 제11권3호
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• pp.189-196
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• 2022

The practical difficulties of construction will impose many restrictions on the structural design, and the construction method can also provide unexpected ideas for solving design problems. Through the discussion of three issues closely related to construction in the structural design of Wuhan Center, this paper illustrates the importance of in-depth consideration of the construction situations in the structural design stage. The topics of "Connection between Embedded Steel Plates in Steel Plate Composite Shear Wall" and "Connection Joint between Outrigger Truss and Core Wall" are about how to facilitate on-site construction by simplifying and optimizing detail design. The topic of "Adjusting Internal Force Distribution by Optimizing Construction Sequence" is about how to make the construction process a tool for structural design.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2004년도 학술대회지
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Journal of the Korea Computer Industry Society
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• 제4권4호
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• pp.613-624
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• 2003

This paper proposes a design for efficient and accurate retrieval of similar image subsequences using the multi-dimensional time warping distance as similarity evaluation tool in image sequence database after building of two indexing structures implemented with priority queue and suffix tree respectively. Receiving query image sequence, at first step, the proposed method searches the candidate set of similar image subsequences in priory queue index structure. If it can not get satisfied results, it retrieves another candidate set in suffix tree index structure at second step. The using of the low-bound distance function can remove the dissimilar subsequence without false dismissals during similarity evaluating process between query image sequence and stored sequences in two index structures.

• Proceedings of the KIEE Conference
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Nuclear Engineering and Technology
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• 제54권12호
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• pp.4560-4570
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• 2022

Dynamic fault tree (DFT) and its related research methods have received extensive attention in safety analysis and reliability engineering. DFT can perform reliability modelling for systems with sequential correlation, resource sharing, and cold and hot spare parts. A technical modelling method of DFT is proposed for modelling ship collision accidents and loss-of-coolant accidents (LOCAs). Qualitative and quantitative analyses of DFT were carried out using the cutting sequence (CS)/extended cutting sequence (ECS) method. The results show nine types of dynamic fault failure modes in ship collision accidents, describing the fault propagation process of a dynamic system and reflect the dynamic changes of the entire accident system. The probability of a ship collision accident is 2.378 × 10^-9 by using CS. This failure mode cannot be expressed by a combination of basic events within the same event frame after an LOCA occurs in a marine nuclear reactor because the system contains warm spare parts. Therefore, the probability of losing reactor control was calculated as 8.125 × 10^-6 using the ECS. Compared with CS, ECS is more efficient considering expression and processing capabilities, and has a significant advantage considering cost.

• Korean Journal of Computational Design and Engineering
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• 제3권4호
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• pp.211-222
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• 1998

Parametric design is an important modeling paradigm in CAD/CAM applications, enabling efficient design modifications and variations. One of the major issues in parametric design is to develop a geometric constraint solver that can handle a large set of geometric configurations efficiently and robustly. In this appear, we propose a new approach to geometric constraint solving that employs a graph-based method to solve the ruler-and-compass constructible configurations and a numerical method to solve the ruler-and-compass non-constructible configurations, in a way that combines the advantages of both methods. The geometric constraint solving process consists of two phases: 1) planning phase and 2) execution phase. In the planning phase, a sequence of construction steps is generated by clustering the constrained geometric entities and reducing the constraint graph in sequence. in the execution phase, each construction step is evaluated to determine the geometric entities, using both approaches. By combining the advantages of the graph-based constructive approach with the universality of the numerical approach, the proposed approach can maximize the efficiency, robustness, and extensibility of geometric constraint solver.

• ETRI Journal
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• 제42권1호
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• pp.101-107
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• 2020

For Korean language processing, morphological analysis is a critical component that requires extensive work. This morphological analysis can be conducted in an end-to-end manner without requiring a complicated feature design using a sequence-to-sequence model. However, the sequence-to-sequence model has a time complexity of O(n²) for an input length n when using the attention mechanism technique for high performance. In this study, we propose a linear-time Korean morphological analysis model using a local monotonic attention mechanism relying on monotonic alignment, which is a characteristic of Korean morphological analysis. The proposed model indicates an extreme improvement in a single threaded environment and a high morphometric F1-measure even for a hard attention model with the elimination of the attention mechanism formula.