• Title/Summary/Keyword: design bias

Search Result 869, Processing Time 0.024 seconds

AN EMPIRICAL BAYESIAN ESTIMATION OF MONTHLY LEVEL AND CHANGE IN TWO-WAY BALANCED ROTATION SAMPLING

  • Lee, Seung-Chun;Park, Yoo-Sung
    • Journal of the Korean Statistical Society
    • /
    • v.32 no.2
    • /
    • pp.175-191
    • /
    • 2003
  • An empirical Bayesian approach is discussed for estimation of characteristics from the two-way balanced rotation sampling design which includes U.S. Current Population Survey and Canadian Labor Force Survey as special cases. An empirical Bayesian estimator is derived for monthly effect under presence of two types of biases and correlations It is shown that the marginal distribution of observation provides more general correlation structure than that frequentist has assumed. Consistent estimators are derived for hyper-parameters in Normal priors.

A Study on an Artificial Neural Network Design using Evolutionary Programming (진화 프로그래밍 기법을 이용한 신경망의 자동설계에 관한 연구)

  • 강신준;고택범;우천희;이덕규;우광방
    • Journal of Institute of Control, Robotics and Systems
    • /
    • v.5 no.3
    • /
    • pp.281-287
    • /
    • 1999
  • In this paper, a design method based on evolutionary programming for feedforward neural networks which have a single hidden layer is presented. By using an evolutionary programming, the network parameters such as the network structure, weight, slope of sigmoid functions and bias of nodes can be acquired simultaneously. To check the effectiveness of the suggested method, two numerical examples are examined. The performance of the identified network is demonstrated.

  • PDF

Design of A Biased Random Vector Generator for A Functional Verification of Microprocessor (마이크로프로세서 기능 검증을 위한 바이어스 랜덤 벡터 생성기 설계)

  • 권오현;양훈모;이문기
    • Proceedings of the IEEK Conference
    • /
    • 2002.06b
    • /
    • pp.273-276
    • /
    • 2002
  • In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the pall which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a Period for verifying function.

  • PDF

Design of A Biased Random Vector Generator for A Functional Verification of Microprocessor (마이크로프로세서 기능 검증을 위한 바이어스 랜덤 벡터 생성기 설계)

  • 권오현;양훈모;이문기
    • Proceedings of the IEEK Conference
    • /
    • 2002.06b
    • /
    • pp.121-124
    • /
    • 2002
  • In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the part which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a period for verifying function.

  • PDF

Design and Realization of High Voltage Operational Amplifier (고전압 연산 증폭기의 설계 및 구현)

  • Kim, Kee-Eun;Jung, Hea-Yong;Cho, Jae-Han;Park, Jong-Sik
    • Proceedings of the KIEE Conference
    • /
    • 2002.11c
    • /
    • pp.517-520
    • /
    • 2002
  • This paper has been studied Operational Amplification Circuit that has high power specification of 90 W is designed. In the input differential amplifier stage, the current source for circuit bias is designed to protect device from high voltage source. the criving state has the voltage gain more than input differential stage. With temperature compensation design, output stage works stable in different to temperature.

  • PDF

Design of mulimeter-wave ultra-compact broadband MMIC amplifiers (밀리미터파 초소형 광대역 MMIC 증폭기 설계에 관한 연구)

  • 권영우
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.22 no.8
    • /
    • pp.1733-1739
    • /
    • 1997
  • An ultra-compact milimeter-wave broadband MMIC amplifier was designed using a direct-coupled topology combined with optimum feedback design. Significant reductionin the chip size was possible by employing the direct-coupled topology. Bias resistors required for the direct-coupled topology were also used as feedback elements. Feedback was optimized for millimeter-wave frequencies using reactive elements. The fabricated MMIC amplifier was realized in a chip size of 0.8mm$^{[-992]}$ and showed gains higher than 8 dB from 12 to 44 GHz. An output power of 30mW was achieved at 44 GHz with a drain efficiency of 10%.

  • PDF

Design of a MOSFET Monostable Multivibrator by Graphical Method (도식방법에 의한 MOSFET 단안정 멀티바이브레이터의 설계)

  • 심수보
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.13 no.1
    • /
    • pp.11-15
    • /
    • 1976
  • In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

  • PDF

Design of CMOS Optical Link Receiver for FTTH (FTTH용 CMOS Optical Link Receiver의 설계)

  • Kim Kyu-Chull
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.1
    • /
    • pp.47-52
    • /
    • 2004
  • This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.2
    • /
    • pp.186-192
    • /
    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

Design and Fabrication of Distributed Analog Phase Shifter Using Ferroelectric $(Ba,\;Sr)TiO_3$ Thin Films (강유전체 $(Ba,\;Sr)TiO_3$ 박막을 이용한 분포 정수형 아날로그 위상 변위기 설계 및 제작)

  • Ryu, Han-Cheol;Moon, Seung-Eon;Lee, Su-Jae;Kwak, Min-Hwan;Lee, Sang-Seok;Kim, Young-Tae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2003.07b
    • /
    • pp.616-619
    • /
    • 2003
  • This work presents the design, fabrication and microwave performance of distributed analog phase shifter (DAPS) fabricated on $(Ba,\;Sr)TiO_3$ (BST) thin films for X-band applications. Ferroelectric BST thin films were deposited on MgO substrates by pulsed laser deposition. The DAPS consists of high impedance coplanar waveguide (CPW) and periodically loaded tunable BST interdigitated capacitors (IDC). In order to reduce the insertion loss of DAPS and to remove the alteration of unloaded CPW properties according to an applied dc bias voltage, BST layer under transmission lines were removed by photolithography and RF-ion milling. The measured results are in good agreement with the simulated results at the frequencies of interest. The measured differential phase shift based on BST thin films was $24^{\circ}$ and the insertion loss decreased from 1.1 dB to 0.7 dB with increasing the bias voltage from 0 to 40V at 10 GHz.

  • PDF