• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.257-258
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• 2011

This paper describes a new method for the seamless operation mode transfer of a PCS with minimized voltage disturbance. The proposed method provides reduced STS turn off time after line fault and smooth mode change between current and voltage control of the PCS. The usefulness of the method is verified through simulations with the consideration of the time delay in detecting a line fault and SCR turn-off time.

• 품질경영학회지
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• 제21권2호
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• pp.17-26
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• 1993

Process fault diagnosis is a complicated matter because quality control problems can result from a variety of causes. These causes include problems with electrical components, mechanical components, human errors, job justification errors, and air conditioning influences. In order to make the system run smoothly with minimum delay, it is necessary to suggest heuristic remedies for the detected faults. Hence, this paper describes a heuristic methodology of fault diagnosis that is performed using statistical patterns generated by quality characteristics The proposed methodology is described briefly as follows: If a sample pattern generated by random variables is similar to the number of prototype patterns, the sample pattern may be matched by any prototype pattern among them to be resembled. This concept is based on the similarity between a sample pattern and the matched prototype pattern. The similarity is calculated as the weighted average of squared deviation, which is expressed as the difference between the relative values of standard normal distribution to be transformed by the observed values of quality characteristics in a sample pattern and the critical values of the corresponding ones in a matched prototype pattern.

• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 C
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• pp.1357-1359
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• 1999

This paper presents fault detection in cables. We developed the device for detecting pinpoint location of faults in power cables using acoustic method. The proposed device consists of hardware and software for the fault detection. Using the device, we explain how to detect the pinpoint of faults and introduce that the other method use the time delay between electro-magnetic and acoustic signals for the pinpoint of the faults.

• 전자공학회논문지B
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• 제31B권9호
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2004년도 춘계학술대회논문집
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• pp.979-984
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• 2004

The ball bearing having faults generally shows, nonlinear vibration characteristics. For the effective method of fault diagnosis on bail bearing, non-linear diagnostic methods can be used. In this paper, the correlation dimension analysis based on nonlinear timeseries was applied to diagnose the faults of ball bearing. The correlation dimension analysis shows some Intrinsic information of underlying dynamical systems, and clear the classification of the fault of ball bearing.

• 전기학회논문지P
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• 제65권3호
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• pp.178-182
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• 2016

FIDVR(Fault Induced Delayed Voltage Recovery) is a phenomenon that recovery of the system voltage level delays after the fault. Cause of FIDVR phenomenon is motor load characteristic about voltage and reactive power. In low voltage condition, the motor go to stall state that consume large amount of reactive power. As a result, the voltage recovery problem is that of repeated occurrences of sustained low voltage following faults on the system. In this paper, analysis the characteristics of the motor load. And using the korean power system actual data, perform a case studies to voltage delay recovery phenomenon alleviation method. Change of each parameters by analyzing the effect on system and selecting an influence parameter. In addition, dynamic characteristic analysis of the resulting difference in the proportion by the motor load in power systems, considering the effect on the voltage stability.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1029-1039
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• 2013

To avoid undesirable disconnection of healthy wind generators (WGs) or a wind power plant, a WG protection relay should discriminate among faults, so that it can operate instantaneously for WG, connected feeder or connection bus faults, it can operate after a delay for inter-tie or grid faults, and it can avoid operating for parallel WG or adjacent feeder faults. A WG protection relay based on the positive- and negative-sequence fault components is proposed in the paper. At stage 1, the proposed relay uses the magnitude of the positive-sequence component in the fault current to distinguish faults requiring non-operation response from those requiring instantaneous or delayed operation responses. At stage 2, the fault type is first determined using the relationships between the positive- and negative-sequence fault components. Then, the relay differentiates between instantaneous operation and delayed operation based on the magnitude of the positive-sequence fault component. Various fault scenarios involving changes in position and type of fault and faulted phases are used to verify the performance of the relay. This paper concludes by implementing the relay on a hardware platform based on a digital signal processor. Results indicate that the relay can successfully distinguish the need for instantaneous, delayed, or non-operation.

• 대한전자공학회논문지SD
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• 제47권2호
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• pp.51-59
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• 2010

드모르간 및 재대입 논리변환은 unate gate network (UGN)을 보다 일반적인 balanced inversion parity (BIP) network으로 전환하는데 충분하다. 이러한 회로계층에 대해서도 자세히 논의하고 있다. 우리는 드모르간 및 재대입 논리변환이 경로지연고장 테스트집합을 유지한다는 것을 증명하였다. 본 논문의 결과를 이용하여 함수 z를 구현하는 모든 UGN에서 모든 경로지연고장을 검출하는 상위수준 테스트집합은 함수 z의 어떠한 BIP realization에서도 모든 경로지연고장을 검출한다는 것을 보일 수 있다.

• 정보처리학회논문지D
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• 제14D권6호
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• pp.649-656
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• 2007

오늘날 차량네트워크(CAN)는 전기적 강인, 저가격과 접근지연 때문에 분산 임베디드 시스템에서 널리 사용되는 버스형 필드이다. 그러나 버스토폴로지에서 발생하는 의존적인 제한 때문에 차량네트워크가 어플리케이션상에서 안전적으로 사용되는지는 논쟁되어왔다. 그래서 차량네트워크(CAN) 디자인 단계 동안 데이터 버스의 부하와 최대 지연, 경쟁 우선순위와 같은 네트워크의 성능을 분석하는 것이 중요하게 되었다. 이 논문은 차량네트워크의 성능을 평가하기 위해 사용된 시뮬레이션 알고리즘과 고장 기법 기술을 적용을 소개한다. 이는 차량네트워크의 어떤 산만한 구현의 줄임과 시스템의 신뢰성을 향상 시켜 줄 것이다.