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Path Delay Test-Set Preservation of De Morgan and Re-Substitution Transformations  

Yi, Joon-Hwan (Computer Engineering, Kwangwoon University)
Lee, Hyun-Seok (Electronics and Communications, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.2, 2010 , pp. 51-59 More about this Journal
Abstract
Two logic transformations, De Morgan and re-substitution, are sufficient to convert a unate gate network (UGN) to a more general balanced inversion parity (BIP) network. Circuit classes of interest are discussed in detail. We prove that De Morgan and re-substitution transformations are test-set preserving for path delay faults. Using the results of this paper, we can easily show that a high-level test set for a function z that detects all path delay faults in any UGN realizing z also detects all path delay faults in any BIP realization of z.
Keywords
path delay fault; test-set preserving; testability; logic transformation; De Morgan; re-substitution;
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Times Cited By KSCI : 1  (Citation Analysis)
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