• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.313-323
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• 2014

Sensor fault detection and isolation problems subject to H_/$H_{\infty}$, performance are concerned for linear time-invariant systems with time delay in a state and parametric uncertainties. To that end, a model-based observer bank approach is pursued. The design conditions for both continuous- and discrete-time cases are formulated in terms of matrix inequalities, which are then converted to the problems solvable via an algorithm involving convex optimization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1639-1651
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• 1998

In this paper, we present analytical and simulation models for evaluating the operation of a uniprocessor computer which utilizes a time redundant approach (such as recomputation by shilted operands) for lault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions 01 each job must be processed. Three methods for appropriately scheduling the primary and sL'Condary versions of the jobs are proposed and analyzed. The proposed scheduling methods take into account the load and the fault rate of the uniprocessor to evaluate two figures of merit for cost and profit with respect to a delay in response time due to faults and fault tolerance. Our model utilizes a fault-tolerant schedule according to which it is possible to find an optimal delay (given by $\kappa$) based on empiric parameters such as cost, the load and the fault rate of the uniprocessor.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.4
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• pp.315-320
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• 2015

This paper describes the implemenation of localization and visualization scheme to find out an ultrasonic source caused by defects of a power distribution line equipment. To increase the fault detection performance, $2{\times}4$ sensor array is configured with MEMS ultrasonic sensors, and from the sensor signals aquired, the azimuth and elevation angles of the ultrasonic source is estimated based on the delay-sum beam forming method. Also, to visualize the estimated location, it is marked on the background image. Experimental results show applicability of the present technique.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.5
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• pp.45-52
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• 2002

This paper presents fault detection scheme of Brushless DC(BLDC) motor drive system by estimating BLDC motor resistance using motor input and output data which is transmitted from data acquisition board to host computer over serial communication channel. Since communication time delay has a serious effect on performance, we use periodic and fixed communication protocol. Hence, the delay time is priory known. Simplified BLDC motor model and recursive least square algorithm is used for estimating motor resistance. By experiment result, we confirm the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.24-24
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• 2001

빠른 반도체 기술의 발전으로 인하여 VLSI 회로의 복잡도는 크게 증가하고 있다. 그래서 복잡한 회로를 테스팅하는 것은 아주 어려운 문제로 대두되고 있다. 또한 집적회로의 증가된 집적도로 인하여 여러 가지 형태의 고장이 발생하게 됨으로써 테스팅은 더욱 중요한 문제로 대두되고 있다. 이제까지 일반적으로 지연 고장 테스팅에 대한 신뢰도는 가정된 고장의 개수에 대한 검출된 고장의 개수로 표현되는 전통적인 고장 검출율로서 평가되었다. 그러나 기존의 교장 검출율은 고장 존재의 유무만을 고려한 것으로써 실제의 지연 고장 테스팅에 대한 신뢰도와는 거리가 있다. 지연 고장 테스팅은 고착 고장과는 달리 경로의 진행 지연과 지연 결함 크기 그리고 시스템 동작 클럭 주기에 의존하기 때문이다. 본 논문은 테스트 중인 경로의 진행 지연과 지연 결함 크기를 고려한 새로운 고장 검출율 메트릭으로서지연 결함 고장 검출율(delay defect fault coverage)을 제안하였으며, 지연 결함 고장 검출율과 결함 수준(defect level)과의 관계를 분석하였다

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.405-407
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• 1994

In order to provide reliable power service and to prevent a potentail hazard and damage, it is important to detect high impedance fault in power distribution line. This paper presents a neural network based approach for the detection of high impedance faults. A time delay neural network has been selected and trained for the fault currents obtained from field experiments. Detection experiments have been performed with the data from four different high impedance surfaces. Experimental results indicated the feasibility of using TDNN for the detection of high impedance faults.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.466-473
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• 2011

This paper proposes a protection algorithm for a wind turbine generator (WTG) in a large wind farm. To minimize the outage section, a protection relay for a WTG should operate instantaneously for an internal fault or a connected feeder fault, whereas the relay should not operate for an internal fault of another WTG connected to the same feeder or an adjacent feeder fault. In addition, the relay should operate with a delay for an inter-tie fault or a grid fault. An internal fault of another WTG connected to the same feeder or an adjacent feeder fault, where the relay should not operate, is determined based on the magnitude of the positive sequence current. To differentiate an internal fault or a connected feeder fault from an inter-tie fault or a grid fault, the phase angle of the negative sequence current is used to distinguish a fault type. The magnitude of the positive sequence current is then used to decide either instantaneous operation or delayed operation. The performance of the proposed algorithm is verified under various fault conditions with EMTP-RV generated data. The results indicate that the algorithm can successfully distinguish instantaneous operation, delayed operation, or non-operation depending on fault positions and types.