• Title/Summary/Keyword: delay cell

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Self-Power Gating Technique For Low Power Asynchronous Circuit

  • Mai, Kim-Ngan Thi;Vo, Huan Minh
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.548-557
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    • 2018
  • In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

Performance analysis of the B-NT system using simulstor (시뮬레이터를 이용한 B-NT 시스템 성능분석)

  • 이규호;기장근;노승환;최진규;김재근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.6
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    • pp.1503-1513
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    • 1998
  • This paper is related to a performance analysis of B-NT system, which is essential compositional equipment of B-ISDN access network. A simulator enabling performance analysis according to the change of network configuration topology and the change of user traffic is developed in this study. The developed B-NT, system simulator consists of graphic user interface module, simulation program automatic generator module, and B-NT system model library module. As examples of the results of performance analysis using the simulator, end-to-end user cell transmission delay time, queueing delay time in each system, and cell loss rate in the head node switch are presented. The simulator developed in this paper can be utilized in determining the network topology of B-NT system.

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The Study on the Dynamic Bandwidth Allocation Algorithm using by Cell Delay Variation (셀지연변이를 이용한 동적 대역폭 할당 알고리즘에 관한 연구)

  • 신승호;박상민
    • Proceedings of the Safety Management and Science Conference
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    • 2000.11a
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    • pp.131-134
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    • 2000
  • Broadband networks are designed to support a wide variety of services with different traffic characteristics and demands for Quality of Services. Bandwidth allocation methods can be classified into two major categories: static and dynamic. In static allocation, bandwidth is allocated only at call setup time and the allocated bandwidth is maintained during a session. In dynamic allocation, the allocated bandwidth is negotiated during a session. The purpose of this paper is to develop policies for deciding and for adjusting the amount of bandwidth requested for a best effort connection over such as ATM networks. This method is to develop such policies that a good trade off between utilization and latency using cell delay variation to the forecast the incoming traffic in the next period. The performances of the different polices are compared by simulations.

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Dynamic Spacer UPC Algorithm Adopting Token Bucket for Traffic Control in ATM Network (토큰 버킷을 적용한 다이나믹 스페이서 UPC 알고리즘)

  • Park, Yong-Goun;Hahn, Hern-Soo
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2008.06a
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    • pp.39-45
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    • 2008
  • ATM망에서 트래픽의 버스트니스를 완화하기 위한 UPC(Usage Parameter Control) 알고리즘을 제안한다. 기존의 다이나믹 스페이서는 그린 토큰이 축적되어 있을 경우 도착하는 셀을 스페이서와 상관없이 네트워크로 셀을 유입시키는 동적인 스페이서 기능을 수행함으로써 CDV(Cell Delay Variation)에 의한 셀을 위반셀로 구별하지 못하고 그대로 통과시키는 단점이 있다. 즉 스페이서 기능을 사용하지 않음으로써 버스트니스해 질 수 있다. 따라서 본 논문에서는 버스트니스를 완화하기 위한 토큰 버킷을 다이나믹 스페이서 이전에 사용함으로써 다이나믹 스페이서의 버스트니스를 완화시키는 토큰 버킷을 적용한 다이나믹 스페이서 UPC 알고리즘을 제안한다.

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Performance-Driven Multi-Levelizer for Multilevel Logic Synthesis (다단 논리합성을 위한 성능 구동형 회로 다단기)

  • 이재흥;정정화
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.11
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    • pp.132-139
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    • 1993
  • This paper presents a new performance-driven multi-levelizer which transforms a two-level description into a boolean network of the multilevel structure satisfied with user's costraints, such as chip area, the number of wires and literals, maximum delay, function level, fanin, fanout, etc.. The performance of circuits is estimated by reference to the informations in cell library through the cell mapping phase, and multi-levelization of circuits is constructed by the decomposition using the kernel and factoring concepts. Here, the saving cost of a common subexpression is defined to the sum of area and delay saved, when it is substituted. The experiments with MCNC benchmarks show the efficiency of the proposed method.

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A Study on the Effect of Propagation Delay Time on Critical Time in Storage Elements (기억논리소자에서의 전달지연시간에 의한 Critical Time의 변화 양상 고찰)

  • Joo, Y.J.;Lee, S.H.;Ryoo, J.H.;Lee, S.H.;Sung, Y.K.
    • Proceedings of the KIEE Conference
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    • 1995.07b
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    • pp.922-924
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    • 1995
  • The modeling of accurate timing in storage elements of ASIC cell library was studied. The propagation delay time of clock signal affects the critical time and this can cause malfunction in the chip designed in synchronous. In this paper, an analysis on the effect of input slope of clock signal in timing modeling were carried out. For the first time, in ASIC design, the design guides that can be used in both $0.6{\mu}M$ and $0.8{\mu}m$ design rule were offered, reducing the run time of SPICE and the time of cell library development.

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The Traffic Control Mechanisms and Performance Analysis of Multimedia Synchronization Cell (멀티미디어 동기셀의 트래픽 제어 기법 및 성능 분석)

  • Jeon, Byeong-Ho;Kim, Tae-Gyun
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.2
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    • pp.305-314
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    • 1996
  • In the paper, we divide the ATM cells generated by multimedia systems that want to transmit multimedia informations over B-ISDN into two categories:i)a media cell with a media information and ii) a synchronization cell with a synchronization information. We induce a media cell loss equation and a synchroni- zation cell loss equation based on probability distribution functions with on-off source as an input traffic model. In order to meet the requirements of real-time and integrity of multimedia informations, multimedia synchronization cells should provide the delay-sensitive and the loss-sensitive requirements. A traffic control mechanism needs to satisfy above requirements. According to the performance evaluation by a traffic control model simulation, we describe both spatial priority for minimizing the synchronization cell loss and temporal priority for reducing the synchronization cell delay must be applied simultaneously.

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Dynamic Reservation Scheme of Physical Cell Identity for 3GPP LTE Femtocell Systems

  • Lee, Poong-Up;Jeong, Jang-Keun;Saxena, Navrati;Shin, Ji-Tae
    • Journal of Information Processing Systems
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    • v.5 no.4
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    • pp.207-220
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    • 2009
  • A large number of phone calls and data services will take place in indoor environments. In Long Term Evolution (LTE), femtocell, as a home base station for indoor coverage extension and wideband data service, has recently gained significant interests from operators and consumers. Since femtocell is frequently turned on and off by a personal owner, not by a network operator, one of the key issues is that femtocell should be identified autonomously without system information to support handover from macrocell to femtocell. In this paper, we propose a dynamic reservation scheme of Physical Cell Identities (PCI) for 3GPP LTE femtocell systems. There are several reserving types, and each type reserves a different number of PCIs for femtocell. The transition among the types depends on the deployed number of femtocells, or the number of PCI confusion events. Accordingly, flexible use of PCIs can decrease PCI confusion. This reduces searching time for femtocell, and it is helpful for the quick handover from macrocell to femtocell. Simulation results show that our proposed scheme reduces average delay for identifying detected cells, and increases network capacity within equal delay constraints.

Frequency of Delayed Diagnosis of Oral Squamous Cell Carcinoma in Pakistan

  • Naseer, Rabia;Naz, Iram;Mahmood, Muhammad Khurram
    • Asian Pacific Journal of Cancer Prevention
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    • v.17 no.11
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    • pp.5037-5040
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    • 2016
  • Objectives: To determine the frequency of delayed diagnosis of oral squamous cell carcinoma in our setup; highlighting factors responsible for any delay and their possible relevance to demographic and diagnostic features. Methods: This cross sectional study of six months duration was conducted in the Oral and Maxillofacial Surgery Department of the Armed Forces Institute of Dentistry, Rawalpindi, Pakistan. A total of 246 patients, both male and female, having a biopsy proven definitive diagnosis of OSCC were included using a consecutive sampling technique. Delay in diagnosis was assessed from the stated period of time from when the patient first noticed symptoms of disease until a definitive diagnosis was made. We concluded delayed diagnosis if this was more than 40 days. Results: The ages of patients ranged from 27 to 60 years with a mean of $46.7{\pm}10.2$ years and a marked male predominance (3.7:1). Delayed diagnosis was observed in 91.5% of cases. However, statistically no significant differences were found with age, gender, marital, education status, household income and time of biopsy. Conclusion: Our primary finding of delayed diagnosis with no prior contact with any health care professional clearly reflects a need of taking urgent measures to avoid serious impacts on morbidity and mortality associated with OSCC.

Comparison and Analysis of Boost Converter Topologies for the DC/DC Converter in Hydrogen Fuel Cell Hybrid Railway Vehicle (수소연료전지 하이브리드 철도차량용 DC/DC 컨버터를 위한 부스트 컨버터 토폴로지 비교 및 분석)

  • Kang, Dong-Hun;Lee, Il-Oun;Lee, Woo-Seok;Yun, Duk-Hyeon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.4
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    • pp.269-278
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    • 2020
  • In this paper, two types of DC/DC converters in a hydrogen fuel cell hybrid railway vehicle system, which serve to charge high-voltage battery and supply power to an inverter for driving a driving motor, were compared and analyzed. A two-level interleaving boost converter and a three-level boost converter were compared and analyzed, and a theoretical design method was proposed to have an efficiency characteristic of over 95%. In addition, a digital controller design method considering the digital phase delay component of DSP (TMS320F28335) is presented. Finally, the validity of the theoretical design of the converter with 20kW power was verified through static and dynamic experiments respectively.