A Study on the Effect of Propagation Delay Time on Critical Time in Storage Elements

기억논리소자에서의 전달지연시간에 의한 Critical Time의 변화 양상 고찰

The modeling of accurate timing in storage elements of ASIC cell library was studied. The propagation delay time of clock signal affects the critical time and this can cause malfunction in the chip designed in synchronous. In this paper, an analysis on the effect of input slope of clock signal in timing modeling were carried out. For the first time, in ASIC design, the design guides that can be used in both $0.6{\mu}M$ and $0.8{\mu}m$ design rule were offered, reducing the run time of SPICE and the time of cell library development.