• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.441-446
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• 2003

Earlier efforts on optical access concentrated on the design of PONs for the collection and distribution portion of the access network. The PON architecture is very simple but it requires a MAC protocol for control of upstream traffic. The MAC protocol must support QoS (Quality of Service) administration function by various traffic class, efficient dynamic bandwidth assignment function, CDV (Ceil Delay Variation) minimization function etc. This paper proposes a dynamic bandwidth assignment algorithm of the MAC protocol for a broadband access network using an Ethernet Passive Optical Network supporting various traffic class. We compare our proposed with MDRR algorithm using simulation, and confirmed that our proposed Request-Counter algorithm produces shorter average cell delay.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.531-542
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• 2002

An input and output buffering ATM switch conventionally operates in either Queueloss mode or Backpressure mode. Recently, a new mode, which is called Hybrid mode, was proposed to overcome the drawbacks of Queueloss mode and Backpressure mode. In Hybrid mode, when both the destined output buffer and the originfted input buffer are full, a cell is dropped. This thesis analyzes the cell loss rate and the cell delay of Queueloss, Backpressure and Hybrid modes in a switch adopting output-port expansion scheme under uniform traffic. Output-port expansion scheme allows only one cell from an input buffer to be switched during one time slot. If several cells switch to a same destined output port, the number of maximum transfer cells is restricted to K (Output-port expansion ratio). The simulation results show that if an offered load is less than 0.9, Hybrid mode has lower cell loss rate than the other modes; otherwise, Queueloss mode illustrates the lowest cell loss rate, which is a different result from previous researches. However, the difference between Hybrid and Queueloss modes is comparably small. As expected, the average cell delay in Backpressure mode is lower than those of Queueloss mode and Hybrid mode, since the cell delay due to the retransmission of higher number of dropped cells in Backpressure mode is not considered.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.67-73
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• 2001

This paper proposes a new scheduling algorithm for broadband ATM access network. The existed scheduling algorithms (Train, Chao. Dynamic scheduling algorithm) have high cell loss rate and waste channel. These proposed mechanism utilize to control of multimedia services based on the quality of service level of the input traffic This paper suggests a functional architecture of scheduling and the scheduling algorithm to satisfy various QoS requirements. The performance measures of interest, namely steady-state cell loss probability and average delay, average delay, are discussed by simulation results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.52-59
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• 1996

The boroadband ISDN will transprot the traffics for a wide range of applications with different quality-of-service (QOS) requirements and the priorit control mechanism is an effective method to support multiple classes of services. This paper proposes a new mechanism to satisfy simultaneously the different levels of cell loss performance for the two classes of heterogeneous nonreal-time ATM traffics as well as the delay and loss requirements of real-time traffics. Its performance is analyzed using the stochastic integral approach with the cell arrivals of input streams modeled as markov modulated poisson processes.

• Journal of the Korea Safety Management & Science
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• v.2 no.4
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• pp.165-176
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• 2000

Broadband networks are designed to support a wide variety of services with different traffic characteristics and demands for Quality of Services. Bandwidth allocation methods can be classified into two major categories： static and dynamic. In static allocation, bandwidth is allocated only at call setup time and the allocated bandwidth is maintained during a session. In dynamic allocation, the allocated bandwidth is negotiated during a session. The purpose of this paper is to develop policies for deciding and for adjusting the amount of bandwidth requested for a best effort connection over such as ATM networks.. This method is to develop such policies that a good trade off between utilization and latency using cell delay variation to the forecast the incoming traffic in the next period. The performances of the different polices are compared by simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.407-410
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• 1999

Viterbi decoder is implemented with a Radix-4 architecture at 0.5$\mu\textrm{m}$ process even though the delay time of standard tell is big and it causes a bigger chip size. As process develops, the delay time of standard cells is getting smaller. Therefore, the requirement of speed and chip size is satisfied by using Radix-2 algorithm to implement Viterbi decoder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.365-369
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• 1998

본 논문은 CDV (Cell Delay Variation) 허용 한계 $\tau$를 지나치게 크게 설정함으로써 발생하는 대역의 비효율성을 줄일 수 있는 새로운 연결 수락 제어 알고리즘을 제시하고자 한다. 제안한 연결 수락 제어 알고리즘은 셀 지연 변이 허용 한계 T의 지나친 설정을 줄이기 위하여 CDV 측정 메커니즘을 사용하고 그리고 ATM 스위치에 심각한 영향을 주는 worst 트래픽을 효과적으로 제어하기 위하여 쉐이퍼를 사용한다. 또한, 제안된 연결 수락 제어 알고리즘의 성능 분석을 위해 기존의 방법과 시뮬레이션을 통해 대역 이용률에 대한 성능 분석을 수행하였다. 그 결과 제안 알고리즘이 대역 이용률에서 기존 방식보다 더 개선되었음을 확인하였다.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.505-507
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• 2005

In this paper, a timing analysis is performed for the CAN-based simulator system for a fuel cell hybrid electric vehicles. The CAN protocol is recently being used for conventional vehicles, however, the network-induced delay can make the in-vehicle network system unstable. This problem may be occurred in the future vehicles because more ECUs are being required than recent vehicles. In order to develop a stable network-based control system, timing analysis is required at the design process. Throughout this analysis, timing parameters that affect transmission delay are examined and an effective method of predicting a sampling time for a stable communication via CAN protocol. In order to show the validityof suggested timing analysis. some experiments are performed using DSPs with CAN module.