• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• Journal of Power Electronics
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• v.13 no.4
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• pp.558-568
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• 2013

In this paper, a new decoupling technique for a flyback inverter using an active power decoupling circuit with auxiliary winding and a novel switching pattern is proposed. The conventional passive power decoupling method is applied to control Maximum Power Point Tracking (MPPT) efficiently by attenuating double frequency power pulsation on the photovoltaic (PV) side. In this case, decoupling capacitor for a flyback inverter is essentially required large electrolytic capacitor of milli-farads. However using the electrolytic capacitor have problems of bulky size and short life-span. Because this electrolytic capacitor is strongly concerned with the life-span of an AC module system, an active power decoupling circuit to minimize input capacitance is needed. In the proposed topology, auxiliary winding defined as a Ripple port will partially cover difference between a PV power and an AC Power. Since input capacitor and auxiliary capacitor is reduced by Ripple port, it can be replaced by a film capacitor. To perform the operation of charging/discharging decoupling capacitor $C_x$, a novel switching sequence is also proposed. The proposed topology is verified by design analysis, simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.2205_2206
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• 2009

Decoupling capacitor는 Power Plane의 특정 주파수 대역에서 Anti-resonance가 발생, 전력 전달에 저해가 될 시에 부착되어 원활한 전력전달을 하기위한 도구로 많이 사용되어 왔다. 하지만 De-cap(Decoupling capacitor)을 어느 위치에 어떤 용량으로 부착하여야 하는지 문제점이 제기되고 이를 해결하기 위해 무작정 설치하여 보는 번거로움이 있었다. 본 문에서는 De-cap의 적절한 사용법에 대한 방법과 Q-factor의 적용법을 제시한다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.486-487
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• 2012

In this paper, novel three-port active power decoupling (APD) method for applying 250[W] micro-inverter. This type using third port for active power decoupling stores the surplus energy and supplies sufficient energy to grid. Conventional decoupling circuit is applied in single phase grid connected micro-inverter especially single-stage configuration like flyback-type DC-AC inverter. In this passive power decoupling method, electrolytic capacitor with large capacitance is needed for decoupling from constant DC power and instantaneous AC power. However the decoupling capacitor is replaced with film capacitor by using APD, thus the overall system can achieve smaller size and long lifespan. Proposed three-port flyback inverter is verified by design and simulation.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.437-438
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• 2007

In this paper a embedded decoupling capacitor design with gap structure will be discussed. A novel structure is modeling and analization by High Frequency Structure Simulator (HFSS). Proposed capacitor have $2m{\times}2m$ in rectangular shape. The film thickness of copper/dielectric film/substrate is respectively 35um/20um/35um. A dielectric layer of BaTiO3/epoxy has the relative permittivity of 25. Compare of the planar decoupling capacitor, capacitance densities of this structure in the range of $55{\mu}F$/mm2 have been obtained with 50um gap while capacitance densities of planar structure $55{\mu}F$/mm2 in the same size. The frequency dependent behavior of capacitors is numerically extracted over a wide frequency bandwidth 500MHz-7GHz. The decoupling capacitor can work at high frequency band increasing the gap size.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1048-1056
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• 2001

Decoupling capacitors are commonly used to reduce the effect of SSN propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs). In this paper, we introduced a simple high frequency measurement and proposed a wideband (50 MHz ∼3 GHz) equivalent circuit model for decoupling capacitor considering high frequency parasitic effects. The proposed model can be easily combined with the SPICE model of power supply planes far SSN analysis. The circuit simulations with the proposed model show good agreement with the measurement results. Also, we expect to accurately analyze the noise reduction effect as a function of value and location using the proposed model of decoupling capacitor.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.137-138
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• 2012

In this paper, three-port flyback inverter with Active Power Decoupling(APD) circuit is analyzed. Conventional flyback inverter with passive power decoupling circuit needs the electrolytic capacitor with large capacitance for decoupling between constant DC power and instantaneous AC power. However the electrolytic capacitor has low lifespan about 50000 to 100000 hours. So the active power decoupling techniques are applied to reduce input capacitance of flyback inverter. Thus the overall system can achieve smaller size and longer lifespan. Proposed three-port flyback inverter is verified by design optimization, simulation and experimental result.