• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.22-28
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• 2007

High PAPR (peak-to-average power ratio) is a major drawback of OFDM (orthogonal frequency division multiplexing) signals. In this paper, a modified SLM (selective mapping) technique that uses erasure decoding of RS (Reed-Solomon) codes is presented. At the transmitter a set of phase sequences are multiplied such that some portions of check symbols in RS-coded OFDM data blocks are phase-rotated. At the receiver, RS decoding is performed with the phase-rotated check symbols being treated as erasures. Hence, there is no need to send side information about the phase sequence selected to transmit for the lowest PAPR. In addition, the estimation process for the selected phase sequence is no longer needed at the receiver, leading to improvement in terms of complexity and performance. To evaluate the performance of this technique, the CCDF (complementary cumulative distribution function) of PAPR, the BER (bit error rate) and the decoding failure probability are compared with those of the previous SLM techniques.

• Journal of IKEEE
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• v.19 no.3
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• pp.455-459
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• 2015

This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.06a
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• pp.57.2-62
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• 1999

Fractal coding is image compression techniques using one of image characteristics self-transformability. In fractal image coding, the encoding process is to select the domain block similar to a range block. The reconstructed image quality of fractal image coding depends on similitude between a range block and the selected domain block. Domain block similar to a range blocks. In fact, the error of the reconstructed image adds up the generated error in encoding process and the generated error in decoding process. But current domain block estimating function considered only the encoding error. We propose a domain block estimating function to consider not only the encoding error but also the decoding error. By computer simulation, it was verified to obtain the high quality reconstructed image.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.125-128
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• 2000

The conventional fractal decoding was required a vast amount computational complexity. Since every range blocks was implemented to IFS(iterated function system). In order to improve this, it has been suggested to that each range block was classified to iterated and non-iterated regions. If IFS region is contractive, then it can be performed a fast decoding. In this paper, a searched region of the domain in the encoding is limited to the range region that is similar with the domain block, and IFS region is a minimum. So, it can be performed a fast decoding by reducing the computational complexity for IFS in fractal image decoding.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• Journal of Communications and Networks
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• v.6 no.3
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• pp.209-215
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• 2004

In this paper, a butterfly Log-MAP decoding algorithm for turbo code is proposed. Different from the conventional turbo decoder, we derived a generalized formula to calculate the log-likelihood ratio (LLR) and drew a modified butterfly states diagram in 8-states systematic turbo coded system. By comparing the complexity of conventional implementations, the proposed algorithm can efficiently reduce both the computations and work units without bit error ratio (BER) performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1156-1162
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• 1999

In this paper, the problem of decoding transmitted data sequence with diversity reception in the presence of nondelective fading is studied. The expection maximizaton (EM) algorithm is employed to derive an interactive algorithm. The algorithm performs block-by-block coherent decoding with the aid of pilot symbols. It is shown that the complexity of the algorithm grows linearly as a function of sequence length. The performance of the algorithm is shown to better than that of the conventional pilot symbol aided (PSI) algorithm. Simulation results are presented to assess the performance of the algorithm and the results are compared with that of the conventional PSI alforithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Journal of the Korea Society of Computer and Information
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• v.22 no.6
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• pp.17-24
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• 2017

In recent digital broadcasting, up to 250 channels are multiplexed and transmitted. The channel transmission is made in the form of MPEG-2 Transport Stream (TS) and transmits one channel (Video, Audio). In order to check if many broadcast channels are transmitted normally, in multi-channel multi-view system, ability of real-time monitoring is required. In order to monitor efficient multi-channel, a distributed system in which functions and load are distributed should be implemented. In the past, we used an inefficient system that gave all of the functionality to a piece of hardware, which limited the channel acceptance and required a lot of resources. In this paper, we implemented a distributed multi-view system which can reduce resources and monitor them economically through efficient function and load balancing. It is able to implement efficient system by taking charge of decoding, resizing and encoding function in specific server and viewer function in separate server. Through this system, the system was stabilized, the investment cost was reduced by 19.7%, and the wall monitor area was reduced by 52.6%. Experimental results show that efficient real-time channel monitoring for multi-channel digital broadcasting is possible.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.718-724
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• 2008

We present a novel joint barcode deblurring and nonuniform illumination compensation algorithm for barcode signals whose number of modules is known. The proposed algorithm is based on a penalized least squares method using a roughness penalty function for an illumination model and a double well penalty function for a barcode signal model. In simulations, the proposed method shows an improved performance compared with a conventional method without compensating nonuniform illumination effects. In addition, the proposed method converges quickly during optimization(within 15 iterations), thereby showing strong possibility for real time decoding of barcode signals.