• Title/Summary/Keyword: decoding code

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Upper Bounds for the Performance of Turbo-Like Codes and Low Density Parity Check Codes

  • Chung, Kyu-Hyuk;Heo, Jun
    • Journal of Communications and Networks
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    • v.10 no.1
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    • pp.5-9
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    • 2008
  • Researchers have investigated many upper bound techniques applicable to error probabilities on the maximum likelihood (ML) decoding performance of turbo-like codes and low density parity check (LDPC) codes in recent years for a long codeword block size. This is because it is trivial for a short codeword block size. Previous research efforts, such as the simple bound technique [20] recently proposed, developed upper bounds for LDPC codes and turbo-like codes using ensemble codes or the uniformly interleaved assumption. This assumption bounds the performance averaged over all ensemble codes or all interleavers. Another previous research effort [21] obtained the upper bound of turbo-like code with a particular interleaver using a truncated union bound which requires information of the minimum Hamming distance and the number of codewords with the minimum Hamming distance. However, it gives the reliable bound only in the region of the error floor where the minimum Hamming distance is dominant, i.e., in the region of high signal-to-noise ratios. Therefore, currently an upper bound on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix cannot be calculated because of heavy complexity so that only average bounds for ensemble codes can be obtained using a uniform interleaver assumption. In this paper, we propose a new bound technique on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix using ML estimated weight distributions and we also show that the practical iterative decoding performance is approximately suboptimal in ML sense because the simulation performance of iterative decoding is worse than the proposed upper bound and no wonder, even worse than ML decoding performance. In order to show this point, we compare the simulation results with the proposed upper bound and previous bounds. The proposed bound technique is based on the simple bound with an approximate weight distribution including several exact smallest distance terms, not with the ensemble distribution or the uniform interleaver assumption. This technique also shows a tighter upper bound than any other previous bound techniques for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix.

The Softest handoff Design using iterative decoding (Turbo Coding)

  • Yi, Byung-K.;Kim, Sang-G.;Picknoltz, Raymond-L.
    • Journal of Communications and Networks
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    • v.2 no.1
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    • pp.76-84
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    • 2000
  • Communication systems, including cell-based mobile communication systems, multiple satellite communication systems of multi-beam satellite systems, require reliable handoff methods between cell-to-cell, satellite-to-satellite of beam-to-team, respectively. Recent measurement of a CDMA cellular system indicates that the system is in handoff at about 35% to 70% of an average call period. Therefore, system reliability during handoff is one of the major system performance parameters and eventually becomes a factor in the overall system capacity. This paper presents novel and improved techniques for handoff in cellular communications, multi-beam and multi-satellite systems that require handoff during a session. this new handoff system combines the soft handoff mechanism currently implemented in the IS-95 CDMA with code and packet diversity combining techniques and an iterative decoding algorithm (Turbo Coding). the Turbo code introduced by Berrou et all. has been demonstrated its remarkable performance achieving the near Shannon channel capacity [1]. Recently. Turbo codes have been adapted as the coding scheme for the data transmission of the third generation international cellular communication standards : UTRA and CDMA 2000. Our proposed encoder and decoder schemes modified from the original Turbo code is suitable for the code and packet diversity combining techniques. this proposed system provides not only an unprecedented coding gain from the Turbo code and it iterative decoding, but also gain induced by the code and packet diversity combining technique which is similar to the hybrid Type II ARQ. We demonstrate performance improvements in AWGN channel and Rayleigh fading channel with perfect channel state information (CSI) through simulations for at low signal to noise ratio and analysis using exact upper bounding techniques for medium to high signal to noise ratio.

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LDPC Generation and Decoding concatenated to Viterbi Decoder based on Sytematic Convolutional Encoder (길쌈부호기를 이용한 LDPC 패리티검사 행렬생성 및 비터비 복호 연계 LDPC 복호기)

  • Lee, Jongsu;Hwang, Eunhan;Song, Sangseob
    • Smart Media Journal
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    • v.2 no.2
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    • pp.39-43
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    • 2013
  • In this paper, we suggest a new technique for WPC parity-check matrix (H-matrix) generation and a corresponding decoding process. The key idea is to construct WPC H-matrix by using a convolutional encoder. It is easy to have many different coderates from a mother code with convolutional codes. However, it is difficult to have many different coderates with LDPC codes. Constructing LDPC Hmatrix based on a convolutional code can easily bring the advantage of convolutional codes to have different coderates. Moreover, both LDPC and convolutional decoding algorithms can be applied altogether in the decoding part. This process prevents the performance degradation of short-length WPC code.

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High Speed Turbo Product Code Decoding Algorithm (고속 Turbo Product 부호 복호 알고리즘 및 구현에 관한 연구)

  • Choi Duk-Gun;Lee In-Ki;Jung Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.6C
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    • pp.442-449
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    • 2005
  • In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.

Adaptive Hard Decision Aided Fast Decoding Method in Distributed Video Coding (적응적 경판정 출력을 이용한 고속 분산 비디오 복호화 기술)

  • Oh, Ryang-Geun;Shim, Hiuk-Jae;Jeon, Byeung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.6
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    • pp.66-74
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    • 2010
  • Recently distributed video coding (DVC) is spotlighted for the environment which has restriction in computing resource at encoder. Wyner-Ziv (WZ) coding is a representative scheme of DVC. The WZ encoder independently encodes key frame and WZ frame respectively by conventional intra coding and channel code. WZ decoder generates side information from reconstructed two key frames (t-1, t+1) based on temporal correlation. The side information is regarded as a noisy version of original WZ frame. Virtual channel noise can be removed by channel decoding process. So the performance of WZ coding greatly depends on the performance of channel code. Among existing channel codes, Turbo code and LDPC code have the most powerful error correction capability. These channel codes use stochastically iterative decoding process. However the iterative decoding process is quite time-consuming, so complexity of WZ decoder is considerably increased. Analysis of the complexity of LPDCA with real video data shows that the portion of complexity of LDPCA decoding is higher than 60% in total WZ decoding complexity. Using the HDA (Hard Decision Aided) method proposed in channel code area, channel decoding complexity can be much reduced. But considerable RD performance loss is possible according to different thresholds and its proper value is different for each sequence. In this paper, we propose an adaptive HDA method which sets up a proper threshold according to sequence. The proposed method shows about 62% and 32% of time saving, respectively in LDPCA and WZ decoding process, while RD performance is not that decreased.

LLR Based Generalization of Soft Decision Iterative Decoding Algorithms for Block Turbo Codes (LLR 기반 블록 터보 부호의 연판정 복호 알고리즘 일반화)

  • Im, Hyun-Ho;Kwon, Kyung-Hoon;Heo, Jun
    • Journal of Broadcast Engineering
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    • v.16 no.6
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    • pp.1026-1035
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    • 2011
  • This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

MTA(Memory TestAble) Code for Testing in Semiconductor Memories (반도체 메모리의 테스트를 위한 MTA(Memory TestAble code)코드)

  • 이중호;조상복
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.8
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    • pp.111-121
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    • 1994
  • This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

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A performance analysis of layered LDPC decoder for mobile WiMAX system (모바일 WiMAX용 layered LDPC 복호기의 성능분석)

  • Kim, Eun-Suk;Kim, Hae-Ju;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.4
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    • pp.921-929
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    • 2011
  • This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

High-Speed Decoding Algorithm of Data Codeword in Two-Dimensional PDF417 Bar Code (이차원 PDF417 바코드에서 데이터 코드워드의 고속 디코딩 알고리즘)

  • Kim, Young-Jung;Cho, Young-Min;Lee, Jong-Yun
    • Journal of Digital Convergence
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    • v.12 no.2
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    • pp.285-293
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    • 2014
  • Two-dimensional PDF417 bar code has a wide range of use and has a storage capacity to compress a large amount of data. With these characteristics, PDF417 has been used in various ways to prevent the forgery and alteration of important information in documents. On the other hand, previous decoding methods in PDF417 barcode are slow and inefficient because they simply employ the standard specifications of AIM (Association for Automatic Identification and Mobility). Therefore, this paper propose an efficient and fast algorithm of decoding PDF417 bar code. As a result, the proposed decoding algorithm will be more faster and efficient than previous methods.

Design of a Variable Shortened and Punctured RS Decoder (단축 및 펑처링 기반의 가변형 RS 복호기 설계)

  • Song Moon-Kyou;Kong Min-Han;Lim Myoung-Seob
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.8C
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    • pp.763-770
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    • 2006
  • In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.