• Polymer(Korea)
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• v.37 no.2
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• pp.232-239
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• 2013

A series of novel imidazole-blocked diisocyanate bioadhesives (IBAs) were synthesized from reaction of toluene 2, 4-diisocyanate (TDI), isophorone diisocyanate (IPDI), hydroxyl-terminated polylactide (HO-PLA-OH), 1,1,1-trimethylolpropane (TMP), and imidazole. Synthesis of IBAs was confirmed by Fourier transform infrared spectroscopy (FTIR) and gel permeation chromatography (GPC). Differential scanning calorimetry (DSC) and thermal gravimetric analysis (TGA) revealed that the TDI-based IBA had lower thermal dissociation temperature and a faster deblocking rate than IBA based on IPDI. Hydroxyl-terminated polyurethane (HPU) was introduced to study the adhesive effect of the synthesized IBAs. Improvement on elastic modulus, tensile strength and water resistance of IBA-modified HPU in comparison with neat HPU suggested the good adhesive effect of IBA due to the strong chemical reaction between released NCO groups from IBA and hydroxyl groups from HPU.

• Macromolecular Research
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• v.13 no.5
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• pp.427-434
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• 2005

To improve the performance and reduce raw material costs, blocked isocyanates were prepared with mixture of blocking agents in many industries. Three blocked isocyanates (adducts) namely $\varepsilon$-caprolactam/benzotriazole-blocked 4,4'-diphenylmethane diisocyanate (MDI), toluene-2,4-diisocyanate (TDI) and 4,4'-dicyclohexyl-methane diisocyanate ($H_{12}$MDI) were synthesized. Six reference adducts were also prepared by blocking MDI, TDI, and $H_{12}$MDI with $\varepsilon$-caprolactam ($\varepsilon$-CL) or benzotriazole. The reactions were carried out in acetone medium and dibutyltin dilaurate (DBTDL) was used as a catalyst. The progress of the blocking reaction was monitored by IR spectroscopy. De-blocking temperatures (dissociation temperatures) of these adducts were studied using DSC and TGA and the results were correlated. As expected, the thermal analysis data showed that de-blocking temperature of blocked aromatic isocyanates was lower than that of the blocked aliphatic isocyanates. The low de-blocking temperature of blocked aromatic isocyanate could be due to electron withdrawing benzene ring present in the blocked isocyanates. It was also found that benzotriazole-blocked adducts de-blocked at higher temperature compared with $\varepsilon$-CL-blocked adducts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10A
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• pp.1011-1020
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• 2002

The current paper presents an effective deblocking algorithm for block-based coded images using singularity detection in a wavelet transform. In block-based coded images, the local maxima of a wavelet transform modulus detect all singularities, including blocking artifacts, from multiscale edges. Accordingly, the current study discriminates between a blocking artifact and an edge by estimation the Lipschitz regularity of the local maxima and removing the wavelet transform modulus of a blocking artifact that has a negative Lipschitz regularity exponent. Experimental results showed that the performance of the proposed algorithm was objectively and subjectively superior.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.617-630
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• 2010

At 37th VCEG meeting in Jan. 2009, Toshiba proposed Quadtree-based Adaptive Loop Filter (QALF). The basic concept of QALF is to apply Wiener filter to decoded image after the conventional deblocking filter and to represent the filter on/off flag data for each basic filtering unit in a more efficient way of quadtree structure. QALF could enhance the compression performance of around more than 9%, but the structure of one filter for a decoded frame leaves room for further improvement in the sense that optimal filter for one region of a frame could quite different from the optimal filter for other parts of a picture. This paper proposes multiple adaptive loop filters for better utilization of local characteristics of decoded frame to optimize the region-based Wiener filters. Additional filters, proposed in this paper, cover separate spatial area of each decoded frame according to the performance of previously designed filter(s) to provide the flexibility of rate-distortion based selection of the number of filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.786-791
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• 2012

This paper presents a depth boundary sharpening method for improved view synthesis in 3D video. In depth coding, distortion occurs around object boundaries, degrading the quality of synthesized images. In order to encounter this problem, the proposed method estimates an edge map for each frame to filter only the boundary regions. In particular, a window-based filter is employed to choose the most reliable pixel as the replacement considering three factors: frequency, similarity and closeness. The proposed method was implemented as post-processing of the deblocking filter in JMVC 8.3.Compared to the conventional methods, the proposed method generated 0.49 dB PSNR increase and 16.58% bitrate decrease on average. The improved portions were subjectively confirmed as well.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.383-391
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• 2005

In this paper, a new anisotropic diffusion based on Alvarez, Lions, and Morel (ALM) diffusion model is proposed for the suppression of blocking artifact caused by discrete cosine transform (DCT) based image compression. The proposed diffusion model, which incorporates a 'rate control parameter' (RCP), makes it possible to reduce blocking artifacts while to preserve the edge. The RCP controls the rate between isotropic and anisotropic diffusion. Isotropic diffusion is encouraged to eliminate the blocking artifacts in a block boundary of a smooth region, while anisotropic diffusion is encouraged to keep the edge or texture sharp in edge and a block boundary within an edge region. Additionally, to avoid oversmoothness of the texture region, a 'speed control parameter' (SCP), which makes diffusion process slow in the texture region, is employed.

• Journal of Korea Multimedia Society
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• v.12 no.11
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• pp.1563-1571
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• 2009

In this paper, we propose a new boundary matching method for the temporal error concealment and a post processing algorithm for perceptual quality improvement of the concealed frame. Temporal error concealment is a method that substitutes error blocks with similar blocks from the reference frame. In conventional H.264/AVC standard, it compares outside pixels of erroneous block with inside pixels of reference block to find the most similar block. However, it is very possible that the conventional method substitutes erroneous block with the wrong one because it compares only narrow spatial range of pixels. In this paper, for substituting erroneous blocks with more correct blocks, we propose enhanced boundary matching method by comparing inside and outside pixels of reference block with outside pixels of erroneous block and setting up additional candidate motion vector in the fixed search range based on maximum and minimum value of candidate motion vectors. Furthermore, we propose a post processing method to smooth edges between concealed and decoded blocks without error by using the modified deblocking filter. We identified that the proposed method shows quality improvement of about 0.9dB over the conventional boundary matching methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.