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Optimized Hardware Design of Deblocking Filter for H.264/AVC  

Jung, Youn-Jin (Department of Information and Communication Engineering, Hanbat National University)
Ryoo, Kwang-Ki (Department of Information and Communication Engineering, Hanbat National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.1, 2010 , pp. 20-27 More about this Journal
Abstract
This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.
Keywords
H.264/AVC;
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