• Title/Summary/Keyword: ddr

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Acceleration Method of RAID Level 5 for DDR-SSD (DDR-SSD를 위한 RAID 레벨 5의 고속화 방법)

  • Gu, Bon-Gen;Kwak, Yun-Sik;Jeong, Seung-Kook;Hwang, Jung-Yeon
    • Journal of Advanced Navigation Technology
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    • v.13 no.5
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    • pp.684-690
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    • 2009
  • In this paper, we propose the acceleration method of the DDR-SSD RAID level 5. The DDR-SSD is the storage device of the Next Generation Storage(NGS) system. The DDR-SSD has different characteristics with HDD and Flash SSD. That's why the DDR-SSD RAID level 5 does not provide the best performance when the normal acceleration method is used. In this paper, to accelerate the DDR-SSD RAID level 5 operation, we propose the parity cache and the architecture of the parity cell. The parity cache stores only parity blocks. This acceleration method proposed in this paper reduce the number of the disk access and the overhead of parity operations.

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Optimization of FPGA-based DDR Memory Interface for better Compatibility and Speed (호환성 및 속도 향상을 위한 FPGA 기반 DDR 메모리 인터페이스의 최적화)

  • Kim, Dae-Woon;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.12
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    • pp.1914-1919
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    • 2021
  • With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

The Evaluation of CR and DDR chest image using ROC analysis (ROC평가 방법을 이용한 CR과 DDR 흉부 영상의 비교)

  • Park, Yeon-Ok;Jung, Eun-Kyung;Park, Yeon-Jung;Nam, So-Ra;Jung, Ji-Young;Kim, Hee-Joung
    • Journal of the Korean Society of Radiology
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    • v.1 no.1
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    • pp.25-30
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    • 2007
  • ROC(Receiver Operating Characteristic)curve is the method that estimate detected insignificant signal from the human's sense of sight, it has been raised excellent results. In this study, we evaluate image quality and equipment character by obtaining a chest image from CR(Computed Radiography) and DDR(Direct Digital radiography) using the human chest phantom, The parameter of exposure for obtaining chest image was 120 kVp/3.2 mAs and the SID(Source to Image Distance) was 180cm. The images were obtained by CR(AGFA MD 4.0 General plate, JAPAN) and DDR(HOLOGIC nDirect Ray, USA). Using some pieces of Aluminum and stone for expressing regions, then attached them on the heart, lung and thoracic vertebrae of the phantom. 29 persons hold radiology degrees were participated in ROC analysis. As a result of the ROC analysis, TPF(true positive fraction) and FPF(false positive fraction) of DDR and CR are 0.552 and 0.474 and 0.629 and 0.405, respectively. By using the results, the ROC curve of CR has higher image quality than DDR. According to the theory, DDR has the higher image quality than CR in chest X-ray image. But, CR has the higher image quality than DDR. quality of DDR inserted the enhance board. The results confirmed that image post-processing is important element decipherment of clinical.

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Device Description Repository System Based on DDR Simple API

  • Cho, Yong-Soon;Lee, Young-Il;Jung, Hoe-Kyung
    • Journal of information and communication convergence engineering
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    • v.7 no.2
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    • pp.203-208
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    • 2009
  • Recently, improved capabilities of the mobile device is represented in a demand for same level services with the desktop device services but the service that is developed for desktop device is not compatible with mobile devices. To fulfill these demands, it is needed to provide services with considering features of mobile devices. This means that CP(Contents Provider) must do contents transformation in order to make suitable contents on mobile device. For managing some information that is required to do contents transformation, we need the DDR(Device Description Repository) which can store and search a variety of device information to grasp the constraints on the mobile device as compared with desktop devices. Also, defining standard API is required to offer a service regardless of platforms. Hereupon W3C(World Wide Web Consortium) introduced DDR Simple API. However that specifies the limited functions of DDR, which is inevitable to be added for more precise search services. In this paper, we expanded DDR Simple API and implemented DDR that supports DDL(Device Description Language) conversion and storing and searching device information.

Performance Analysis of Parity Cache enabled RAID Level 5 for DDR Memory Storage Device (패리티 캐시를 이용한 DDR 메모리 저장 장치용 RAID 레벨 5의 성능 분석)

  • Gu, Bon-Gen;Kwak, Yun-Sik;Cheong, Seung-Kook;Hwang, Jung-Yeon
    • Journal of Advanced Navigation Technology
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    • v.14 no.6
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    • pp.916-927
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    • 2010
  • In this paper, we analyze the performance of the parity cache enabled RAID level-5 via the simulation. This RAID system consists of the DDR memory-based storage devices. To do this, we develop the simulation model and suggest the basic performance analysis data which we want to get via the simulation. And we implement the simulator based on the simulation model and execute the simulator. From the result of the simulation, we expect that the parity cache enabled RAID level-5 configured by the DDR memory based storage devices has the positive effectiveness to the enhancing of the storage system performance if the storage access patterns of applications are tuned.

MiR-199a/b-5p Inhibits Lymphangiogenesis by Targeting Discoidin Domain Receptor 1 in Corneal Injury

  • Oh, Sooeun;Seo, Minkoo;Choi, Jun-Sub;Joo, Choun-Ki;Lee, Suk Kyeong
    • Molecules and Cells
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    • v.41 no.2
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    • pp.93-102
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    • 2018
  • Discoidin domain receptor 1 (DDR1) is involved in tumorigenesis and angiogenesis. However, its role in lymphangiogenesis has been unknown. Here, we tested whether downregulation of DDR1 expression by miR-199a/b can suppress lymphangiogenesis. We also aimed to identify miRNA target site(s) in the 3' untranslated region (UTR) of DDR1. Transfection with miR-199a/b-5p mimics reduced expression of DDR1 and tube formation in primary human dermal lymphatic endothelial cells, whereas miR-199a/b-5p inhibitors showed the opposite effects. Critically, injection of miR-199a/b-5p mimics suppressed DDR1 expression and lymphangiogenesis in a corneal alkali-burn rat model. The three well-conserved seed matched sites for miR-199a/b-5p in the DDR1 3'-UTR were targeted, and miRNA binding to at least two sites was required for DDR1 inhibition. Our data suggest that DDR1 promotes enhanced lymphangiogenesis during eye injury, and miR-199a/b-5p suppresses this activity by inhibiting DDR1 expression. Thus, this miRNA may be useful for the treatment of lymphangiogenesis-related eye diseases.

Distribution of ddr (DNA damage response) Genes among Species of Deinococcus

  • Lim, Sangyong;Jung, Sunwook;Joe, Minho;Kim, Dongho
    • Journal of Radiation Industry
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    • v.4 no.3
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    • pp.289-295
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    • 2010
  • The bacterium Deinococcus radiodurans is one of the most resistant organisms to the effects of ionizing radiation and other DNA-damaging agents. In this study, distributions of 10 ddr (DNA damage response) genes were investigated in 8 species of Deinococcus by polymerase chain reaction (PCR). We have compared the sequences of ddr genes of D. radiodurans, D. geothermalis and D. deserti, and selected primers which are suitable for the detection of ddr in different species of Deinococcus. A sequence homology search and PCR assay showed that ddrO, which encodes a global regulator of the radiation-desiccation response, was most well conserved in the Deinococcus lineage.

Expression of DDR1 and DVL1 in Invasive Ductal and Lobular Breast Carcinoma does not Correlate with Histological Type, Grade and Hormone Receptor Status

  • Ameli, Fereshteh;Rose, Isa Mohd;Masir, Noraidah
    • Asian Pacific Journal of Cancer Prevention
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    • v.16 no.6
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    • pp.2385-2390
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    • 2015
  • Background: Invasive ductal (IDC) and lobular (ILC) carcinomas are the common histological types of breast carcinoma which are difficult to distinguish when poorly differentiated. Discoidin domain receptor (DDR1) and Drosophila dishevelled protein (DVL1) were recently suggested to differentiate IDC from ILC. Objectives: To assess the expression of DDR1 and DVL1 and their association with histological type, grading and hormonal status of IDC and ILC. Materials and Methods: This cross sectional study was conducted on IDC and ILC breast tumours. Tumours were immunohistochemically stained for (DDR1) and (DVL1) as well as estrogen receptor (ER), progesterone receptor (PR) and C-erbB2 receptor. Demographic data including age and ethnicity were obtained from patient records. Results: A total of 51 cases (30 IDCs and 21 ILCs) were assessed. DDR1 and DVL1 expression was not significantly associated with histological type (p=0.57 and p=0.66 respectively). There was no association between DDR1 and DVL1 expression and tumour grade (p=0.32 and p=1.00 respectively), ER (p=0.62 and 0.50 respectively), PR (p=0.38 and p=0.63 respectively) and C-erbB2 expression (p=0.19 and p=0.33 respectively) in IDC. There was no association between DDR1 and DVL1 expression and tumour grade (p=0.52 and p=0.33 respectively), ER (p=0.06 and p=0.76 respectively), PR (p=0.61 and p=0.43 respectively) and C-erbB2 expression (p=0.58 and p=0.76 respectively) in ILC. Conclusions: This study revealed that DDR1 and DVL1 are present in both IDC and ILC regardless of the tumour differentiation. More studies are needed to assess the potential of these two proteins in distinguishing IDC from ILC in breast tumours.

High Speed Data Processing Unit Development Using Xilinx GTP Interface and DDR-2 Memory (Xilinx GTP 인터페이스와 DDR-2 메모리를 이용한 고속 데이터 처리 유닛 개발에 관한 연구)

  • Seo, In-Ho;Oh, Dae-Soo;Lee, Jong-Ju;Park, Hong-Young;Jung, Tae-Jin;Park, Jong-Oh;Bang, Hyo-Choong;Yu, Yong-Ho;Yoon, Jong-Jin;Cha, Kyung-Hwan
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.8
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    • pp.816-823
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    • 2008
  • This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

Synthesis of Deadlock-Free Ladder Diagrams for PLCs Based on Deadlock Detection and.Recovery (DDR) Algorithm (DDR 알고리즘에 기반한 교착상태배제 래더 다이어그램 설계)

  • Cha, Jong-Ho;Cho, Kwang-Hyun
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.8
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    • pp.706-712
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    • 2002
  • In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.