• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.221-229
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• 2004

We present new digital watermarking scheme that embeds a watermark according to the characteristics of the image or video. The scheme is compatible with established image compression standard. We define a weighting function using a parent-child structure of the DCT coefficients in a block to embed a maximum watermark. The spatio-frequency localization of the DCT coefficients can be achieved with this structure. In the detection stage, we present an optimum a posteriori threshold with a given false detection error probability based on the statistical analysis. Simulation results show that the proposed algorithm is efficient and robust against various signal processing techniques. Especially, they are robust against widely used coding standards, such as JPEG and MPEG.

• Korean Journal of Microbiology
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• v.47 no.2
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• pp.174-178
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• 2011

In Escherichia coli, DcuS/R two-component system controls fumarate import and utilization related gene expression. To understand the dynamic response of the bacterium DcuS/R two-component system with respect to fumarate concentrations, DcuS/R induced dctA promoter was integrated with GFP reporter protein. Expression monitoring study using recombinant strain showed that dctA promoter was upregulated with 1 mM of fumarate in M9 minimal medium.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.73-78
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• 2005

Images coded by DCT based compression contain several quality degradations by quantization process. Among them contrast distortion is the important one because human eyes are sensitive to contrast. In case of low bit-rate coded image, we can not get an image having good quality due to quantization error. In this paper, we suggest a new scheme to enhance image's contrast in DCT domain. Proposed method enhances only edge regions. Homogeneous regions are not considered in this method. $8{\times}8$ DCT coefficient blocks are decomposed to $4{\times}4$ sub-blocks for detail edge region discrimination. we could apply this scheme to real-time application because proposed scheme is DCT based method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1714-1719
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• 2011

High quality image processing schemes are used more widely than ever according to the development of various visual media. We need a compressed form of image for sending more capacity and a controlling strategy of images for small display devices. In this paper, we propose an image upsampling and downsamplig scheme using DCT coefficients for those purposes. Our scheme is designed to control the size of picture based on the target display media by reducing the data in DCT domain while not increasing the computational burdens. With the power of controlling the resolution in DCT domain, the proposed method shows higher PSNR than other competing methods in experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2019.11a
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• pp.246-248
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• 2019

In the ongoing standardization of Versatile Video Coding (VVC), DCT-2, DST-7 and DCT-8 are accounted as the vital transform kernels. While storing all of those transform kernels, ROM memory storage is considered as the major problem. So, to deal with this scenario, a common sparse unified matrix concept is introduced in this paper. From the proposed matrix, any point transform kernels (DCT-2, DST-7, DCT-8, DST-4 and DCT-4) can be achieved after some mathematical computation. DCT-2, DST-7 and DCT-8 are the used major transform kernel in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.47-56
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• 1993

In this paper, pyramidal VQ image coding by DCT classifier based on HVS is studied. The proposed DCT classifier based on HVS is that the transform subblocks of the image are mlultiplied by MTF which is a sort of band pass filter and sorted by the magnitude of their ac energy levels and classifeid into three classes such as low, middle and high variance class by the threshold and then edges are detected in comparison of the energy sum of ac transform coefficients corresponding to the different edge directions.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.