• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.162-165
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• 2000

This paper presents the analysis of the effect which DC offsets produced in the direct-conversion receiver system under the AWGN circumstance exercise on the system performance. Then, as a method which improve the system performance by removing the DC offsets, we proposed the plan which can copes with the time variant DC offsets occurrences according to taking accumulation and average through the loop signals which DC offsets are produced.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.221-222
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• 2011

본 논문은 인버터의 PWM구동 시 출력 전류에 발생하는 DC offset을 제거 하는 방법을 제안한다. 인버터의 PWM구동 시 소자 단락을 막기 위해 필수적으로 적용하는 deadtime과 각 스위치 소자의 voltage drop으로 인해 출력에 왜곡이 발생한다. 이상적인 스위치인 경우에는 이 두 가지의 왜곡을 feedforward로 보상하면 된다. 하지만 스위치 소자가 이상적이지 않기 때문에 각 스위치 소자의 voltage drop의 차이와 on & off time delay의 차이는 출력 전류에 DC offset을 발생시킨다. 따라서 deadtime과 스위치 voltage drop에 대한 보상과 함께 출력 전류의 DC offset을 feedback으로 하여 보상되지 못한 왜곡을 추가적으로 보상하여 결론적으로 출력 전류의 DC offset을 제거할 수 있게 하였다. 제안된 기법은 시뮬레이션을 통하여 그 타당성을 확인하였다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.775-779
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• 1999

This paper presents design of AGC(Automatic Gain Control) and DC offset remover suitable for cable modem which makes use of QAM(Quadrature Amplitude Modulation) scheme. Since QAM has multi-level signal characteristic, for high-order QAM, the constellation is dense and the distance of decision boundary between adjacent symbols is short. So AGC and DC offset remover must be designed optionally for preventing performance degradation. AGC is designed into feedback type and is related to the STR(Symbol Timing Recovery)and Paff interpolation algorithm. Whereas AGC need to perform average power detection during many symbols by comparison with the reference power, DC offset remover uses only the instant polarity decision such that simple implementation can be achieved with good performance. Though the AGC and DC offset remover are simulated here only for 256 QAM scheme for convenience'sake, it can be applied to other multi-level QAM or PSK modulation scheme.

• Journal of Power Electronics
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• v.16 no.1
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• pp.310-318
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• 2016

This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.279-286
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• 2006

A method for estimating the instantaneous phasor of a fault current signal is proposed for high-speed distance protection that is immune to a DC-offset. The method uses a modified notch filter in order to eliminate the power frequency component from the fault current signal. Since the output of the modified notch filter is the delayed DC-offset, delay compensation results in the same waveform as the original DC-offset. Subtracting the obtained DC-offset from the fault current signal yields a sinusoidal waveform, which becomes the real part of the instantaneous phasor. The imaginary part of the instantaneous phasor is based on the first difference of the fault current signal. Since a DC-offset also appears in the first difference, the DC-offset is removed trom the first difference using the results of the delay compensation. The performance of the proposed method was evaluated for a-phase to ground faults on a 345kV 100km overhead transmission line. The Electromagnetic Transient Program was utilized to generate fault current signals for different fault locations and fault inception angles. The performance evaluation showed that the proposed method can estimate the instantaneous phasor of a fault current signal with high speed and high accuracy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.900-905
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• 2008

I perform bit error rate(BER) analysis of orthogonal frequency division multiplexing(OFDM) systems impaired by both direct current(DC) offset and carrier frequency offset. By analyzing the BER performance for real OFDM systems employing 16-quadrature amplitude modulation(QAM) and pilot symbol estimation, the dependency of BER on the DC offset and carrier frequency offset is quantified and compared to ideal performance. Results show that the magnitude of frequency offset and DC offset are required to be less than 0.01 and 0.007, respectively.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.422-423
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• 2018

쇄교자속 기반 센서리스 제어는 저속에서 위치 추정 특성이 우수해 낮은 속도의 운전 영역을 가지는 애플리케이션에 많이 쓰인다. 그러나 계측 정보 오차와 모터 파라미터 변동으로 DC-offset이 발생하는 문제가 있다. 이러한 현상을 방지하기 위해 운전 주파수를 고려한 낮은 차단주파수를 갖는 HPF를 사용했으나, 낮은 DC 저감률로 인해 추정 자속에 DC 성분이 남는 문제점이 있다. 따라서 본 논문에서는 HPF의 차단주파수를 모터 운전주파수에 동기화하여 DC-offset 저감률을 높이고 DC-offset이 시스템에 미치는 정도에 따라 선택적으로 차단주파수를 가변함으로써 위상 앞섬도 감소시키는 방법을 제안한다. 제안된 방법은 Matlab/Simulink에 의해 검증된다.

• Journal of Power Electronics
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• v.15 no.2
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.809-814
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• 2012

We propose an adaptive threshold detector algorithm for multi-level holographic data storage based on the expectation-maximization (EM) method. In this paper, the signal intensities that are passed through the four-level holographic channel are modeled as a four Gaussian mixture with unknown DC offsets and the threshold levels are estimated based on the maximum likelihood criterion. We compare the bit error rate (BER) performance of the proposed algorithm with the non-adaptive threshold detection algorithm for various levels of DC offset and misalignments. Our proposed algorithm shows consistently acceptable performance when the DC offset variance is fixed or the misalignments are lower than 20%. When the DC offset varies with each page, the BER of the proposed method is acceptable when the misalignments are lower than 10% and DC offset variance is 0.001.