Switching Voltage Modeling and PWM Control in Multilevel Neutral-Point-Clamped Inverter under DC Voltage Imbalance

Abstract

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

I. INTRODUCTION

Multilevel inverters play an important role in current high-performance applications. Two topologies have become popular in practice, namely, multilevel neutral-point-clamped (NPC) inverter and multilevel cascaded inverter, as shown in Fig. 1. Well-known pulse width modulation (PWM) methods include carrier-based PWM (CPWM) and space vector PWM (SVPWM) techniques [1]-[8].

Fig. 1.Multilevel inverter circuits. (a) Five-level diode-clamped inverter. (b) Five-level cascaded inverter.

In the SVPWM method, the switching states in the switching sequences are selected after determining the three pivot vectors in the space vector diagram. The control process of the SVPWM is relatively complicated in a multilevel inverter [14], [15]. When the inverter level is high, the two main disadvantages of this PWM method are burden calculation and lookup table, both of which require large memory storage.

CPWM techniques are commonly used in practical applications because of their simple implementation. Algorithms of a SVPWM scheme with the nearest three voltage vectors can be completely realized by a corresponding CPWM method.

The offset feature in a two-level inverter has been extensively investigated in previous studies [9]-[11]. In multilevel inverters, a CPWM method can offer flexible control of vector redundancies through proper offset regulation [4], [20].

Offset voltage significantly affects converter performance. Offset adjustments can generate different PWM modes [1], [3], [26]-[31]. Proper selection of offset voltage can reduce switching amount and the harmonic distortion factor in different PWM techniques [4], [24], and its regulation with load currents may minimize switching losses [25]. Therefore, offset voltage is practically indispensable and is an important variable in the control model of a multilevel voltage-source inverter.

Offset control is also available in space vector modulation by redistributing the switching time duties of two redundant states [10]-[13]. However, in multilevel inverters, an algorithm based on the SVPWM method may generally be difficult to apply if the offset is used as a variable to control DC and neutral currents, and thus to balance DC voltages and reduce the effect of common mode voltages (CMVs) on electrical drives [16]-[18].

The unbalanced conditions of DC-link voltages that are fed to an inverter have a negative effect on the output quality. The imbalance, which is represented by the ripple on the DC link, causes distorted output waveforms with low-frequency harmonics. This phenomenon can lead to degradation in the load performance [38]. Solutions to cope with this problem can be found in [19], [23], [35]-[39]. The works in [35]-[37] focused on a two-level inverter and other classic topologies. In [38], a feed-forward SVPWM method was proposed to obtain balanced output voltages in a three-level NPC inverter. Other than the limitation represented by the complication of the control process in this method, the flexibility of the offset voltage has not been fully explored.

In [19], a simple carrier-based method with DC-link ripple feed-forward compensation in a multilevel inverter was introduced. The idea of this work was to modify the carriers according to the DC-link fluctuation. However, given that a sinusoidal reference was assumed and the offset voltage was constant, the maximum modulation index could not be greater than 0.866, which corresponded to the maximum modulation index of the conventional sine PWM method in a balanced condition.

In [23] and [39], a modified SVPWM method was applied to multilevel converters to solve the problem of unbalanced DC conditions. Under balanced and unbalanced conditions, the methods analyzed the control voltage in 3D coordinates and offered a simpler control process than the 2D-SVM in [38]. Nevertheless, the characteristics of the offset were not analyzed. In addition, given that no harmonic injection was considered, the modulation index limitation of 0.866 was unavoidable, as in [19].

The present study proposes a new CPWM technique for multilevel diode-clamped inverters under balanced and unbalanced conditions. The proposed algorithm is applicable to NPC inverters with arbitrary numbers of levels. With the actual conditions of the DC links considered, a novel approach to modeling switching voltages and an offset-based PWM scheme using abc coordinates are systematically analyzed. The switching voltages characterize the control characteristics of multilevel inverters, while the offset-based PWM quality control improves the output quality following some particular demands. In the proposed PWM scheme, the global offset component enables control of the draft CMV, and the local offset component sets the PWM modes. A current-based discontinuous PWM (DPWM) method that utilizes these two offset components to reduce switching loss is also proposed.

The modulation index control has been improved as compared with those in [19], [23], [39]. Therefore, the attainable maximum linear range of the output voltage control (under unbalanced input conditions) is always achieved.

The validity of the proposed feed-forward PWM method will be demonstrated through simulation and experimental results.

 

II. SWITCHING VOLTAGE FORMULATION FOR MULTILEVEL INVERTERS UNDER INPUT VOLTAGE IMBALANCE

A. Modeling of the Switching Voltage for a Multilevel NPC Inverter

In the five-level NPC topology in Fig. 1(a), the DC-link-fed inverter voltages are assumed to have the values V1, V2, V3, and V4. With a selected neutral point “O” and the designated switches in the X-phase (X = A,B,C) represented as SW1X, SW2X, SW3X, and SW4X, respectively, as in Fig. 1(a), the pole (leg) voltage VXO can be determined as

where s1x, s2x, s3x, and s4x represent the switching states of SW1X, SW2X, SW3X, and SW4X, respectively; s1A is “1” if SW1A is ON; otherwise, its value is “0.”

We define the X-phase switching voltage, VSX, (X = A,B,C), which is controlled by switches, as follows:

The switching voltage presents a switching-controlled voltage source to supply the load. Eq. (2) shows that the switching voltage consists of (n − 1) switching voltage components. jth switching voltage component is defined as a product of jth switching state and its corresponding DC voltage cell, that is,

The constraint between switch states for the five-level NPC inverter shown in Fig. 1(a) is simply expressed as

During a sampling period for an X-phase inverter leg, X = A,B,C, only one switch exists, called the active switch sX ; this switch is actively turned on and off. The states of the remaining (n − 2) switches, called the non-active switches, are unchanged (sjX = or 0 sjX = 0). Each non-active switch provides full voltage VSXj = Vj = for sjX = 1 and zero voltage VSXj = 0 for sjX = 0. Among (n − 2) non-active switches, L switches are supposed to hold the ON state, and (n − 2 − L) switches hold the OFF state. We define VLX as the component of the non-active switching voltage provided by the non-active switches. For an active switch sX, if ξX is defined as its average value in a sampling period and VDX as its corresponding DC-link-fed inverter voltage, the instantaneous and average values of the switching voltages can be expressed in terms of two components, namely, non-active switching voltage and active switching voltage. These components are expressed as follows:

The relation among average switching voltage non-active switching voltage VLX and DC voltage linked to active switch VDX can be described as follows:

The instantaneous switching voltage model for a single leg relative to the pole voltage is presented in Fig. 2(a). Fig. 3(b) provides an example of the A-phase switching voltage model in Fig. 2(a) for the case in which switch s2A is active and has a corresponding DC-link-fed inverter voltage V2, and the other non-active switches s1A,s3A,s4A have respective DC-link-fed inverter voltages of V1,V3,V4, which receive values of 0, 1, and 1. The A-phase average voltage model of the example given in Fig. 2(b) is illustrated in Fig. 2(c).

Fig. 2.(a) Relation between A-phase switching voltage and pole voltage. (b) A-phase switching voltage for non-active switches s1A = 0, s3A = 1, s4A = 1 and active switch s2A. (c) Average voltage model of the A-phase switching voltage.

Fig. 3.(a) Average voltage model of the three-phase pole voltages with active switches s2A, s1B, s3C and non-active switches (s1A,s3A,s4A) = (0,1,1), (s2B,s3B,s4B) = (1,1,1), and (s1C,s2C,s4C) = (0,0,1). (b) Average voltage model of the three-phase pole voltages expressed in terms of the fundamental

Eq. (1) indicates that the sum of two DC-link-fed inverter voltages V3,V4 exists in the pole leg voltage formulation. This component presents an offset voltage Voff-DCLink, which is illustrated in the switching voltage model of the five-level NPC inverter in Fig. 2. In topologies with arbitrary numbers of levels, Voff-DCLink an be calculated as the voltage between the neutral point O and the lowest voltage point of the inverter.

The pole voltage VXO can be analyzed in relation to the fundamental output phase voltage as follows:

where

Using Eq. (8) and in consideration of Eq. (1), the instantaneous switching voltage and average switching voltage in a sampling period can be expressed in other forms as follows:

where the reference fundamental output phase voltage and reference CMV respectively. They satisfy

From the one-phase average pole voltage model expressed in terms of average switching voltage and Voff-DCLink as in Fig. 2(c), as well as the average pole voltage obtained in Eq. (11), the three-phase average pole voltage models that use the two analytical approaches are described in Fig. 3. The voltage model in Fig. 3(a) corresponds to a specific case in which the active switches for the A, B, and C phases are s2A, s1B, and s3C, respectively; the sets of non-active switches are (s1A,s3A,s4A) = (0,1,1), (s2B,s3B,s4B) = (1,1,1), and (s1C,s2C,s4C) = (0,0,1).

The relation of the two models in Figs. 3(a) and 3(b) shows that to obtain three-phase output voltages with a predefined CMV, the average switching voltages have to be the sum of the fundamental voltage and a zero sequence voltage injected from the DC-link-fed inverter voltages Voff-DCLink. As a result, a new reference average switching voltage model of the A-phase is derived, as shown in Fig. 4(b). The complete PWM algorithm for multilevel NPC inverters under balanced and unbalanced conditions will be realized by using this switching voltage model and the model illustrated in relation to the active and non-active switching voltages in Fig. 4(a).

Fig. 4.Multilevel NPC inverter: A brief description of the A-phase switching voltage from (a) the active and non-active switching voltage components and (b) the zero/non-zero sequence voltages.

B. Fundamental Voltage Limit and the Global Reference CMV Design

The control limits of two parameters, namely, reference fundamental voltage and CMV, should be determined to completely master the switching voltage model in Fig. 4.

The maximum (minimum) value of the switching voltage will be obtained if all switches are turned “ON” (“OFF”). In a five-level NPC inverter, for example, these values are determined as follows:

As a result, the possible maximum fundamental voltage of the under-modulation limit is given as follows:

The reference CMV can generally be expressed as a function of the variable η1, that is,

where Voff-MX and off Voff-Mn are the maximum and minimum values of respectively. These values can be deduced from the switching voltage model in Fig. 4 and Eqs. (12) and (13) as follows:

The “Min()” function returns the smallest value of the three given values inside the parentheses .

In practical applications, two popular reference average CMV designs are as follows:

Medium CMV [9]–[12]: This CMV approach is often used in two-level and multilevel inverters to maximize the linear PWM control range. In this case, the global offset is obtained by setting η1 = 0.5 in Eq. (15) as follows:

Minimum CMV [25]: The reference offset voltage is selected such that the absolute value of the obtained average CMV is at the minimum. The sinusoidal PWM method is a particular case of this PWM technique for a modulation index range lower than 0.866, that is,

 

III. SWITCHING VOLTAGE IMPLEMENTATION

A. Switching Voltage PWM Control

To implement the reference switching voltages, the active and non-active switching voltage components, as illustrated in Fig. 5(a), have to be calculated. On the basis of Eqs. (4)-(7), the non-active switching voltage components VLX can be simply determined as follows:

where VSXk is the kth discrete switching voltage, and n is the number of levels. For example, in a five-level NPC inverter, five discrete switching voltages are computed in increasing order as VSX1 = 0, VSX2 = V4, VSX3 = V3+V4, VSX4 = V2+V3+V4, and VSX5 = V1+V2+V3+V4.

Fig. 5.Implementation of the active switching voltage switching sequence and the switching time diagram.

The DC-link-fed inverter voltages VDX (X = A,B,C), which correspond to the active switches on the three phases, can be determined as the DC cell between the two nearest discrete switching voltages of

For the active switches, their switching state sequence can be realized by the CPWM approach illustrated in Fig. 5 with the normalized modulating signals ξX, (X = A,B,C), which are calculated as follows:

The switching pattern in Fig. 5, from which the active switching states are directly derived, is similar to that of a two-level inverter. Supposing that in a sampling period the three-phase switching sequence in the first half of the pattern in Fig. 5 is (SA,SB,SC) = (0,0,0) → (1,0,0) → (1,1,0) → (1,1,1), then the corresponding active switching sequence is derived as (0,0,0 → (VDA,0,0) → (VDA,VDB,0) → (VDA,VDB,VDC). The switching voltage sequence is completely realized by using the information of the three-phase non-active voltage and active switching sequence. The switching time diagram of a virtual two level in Fig. 5 is directly imposed onto the switching voltage sequence to complete the switching voltage pattern. As a result, the characteristics of PWM control for a multilevel NPC inverter under unbalanced conditions are fully explored.

When analyzing in the αβ domain of the SVM method, eight switching states of the active switches will establish a voltage vector diagram (Fig. 6). Each discrete voltage vector is calculated as follows:

Fig. 6.Vector diagram of the active switching voltages for (a) balanced DC sources and (b) unbalanced DC sources (VDA>VDB>VDC).

In Fig. 6, the discrete vector denoted as [SA,SB,SC] represents the active switching voltage state (SA.VDA,SB.VDB,SC.VDC). Under an unbalanced condition, the active switching voltage vector diagram forms an asymmetrical hexagon. The zero vector of [000] remains at the center of the old symmetrical hexagon in Fig. 6(a), whereas the zero vector of [111] deviates from its former position. As a result, for a reference vector, the PWM control with the three nearest vector principles cannot be implemented in some regions with minimum switching numbers. For example, when the reference vector has its tip located at point A, as illustrated in Fig. 6(b), the use of the three nearest vectors of [000], [100], and [111] will always require considerable switching. The switch from the continuous PWM mode to DPWM mode by simply removing the vector of [000] or [111] is also not allowed. For example, the active switching voltage vectors of [000]-[100]-[101]-[111] in continuous PWM after removing the vector [111] cannot implement the reference voltage vector in Fig. 6(b) because the area formed by the tips of the remaining vectors of [000]-[100]-[101] does not contain the A point.

B. Active Switching Voltage Control – Design of the Local Offset for Reduced Switching Loss

From the switching voltage model of the multilevel inverter shown in Fig. 4(a), the PWM performance can be improved by modifying the active switching voltages. A new equivalent circuit of the active switching voltages is obtained, as shown in Fig. 7, by adding an offset e0, which is the local offset voltage, to the three-phase average active switching voltages.

Fig. 7.Equivalent circuit of the modified average active switching voltages.

Given that

the modulating signals in Eq. (20) will be modified as follows:

1) Reduced Switching Loss PWM under DC Voltage Imbalance: The control range of the local offset e0 depends on the reference leg voltages of the virtual two-level inverter and the active DC cells of the DC-link-fed inverter voltages. The range can be as follows:

where

The control limits of e0 corresponding to a specific case of VDX and eX (X = A,B,C) are illustrated in Fig. 8.

Fig. 8.Determination of local offset limits from the active voltages and related DC-link voltages.

From Eqs. (24)–(26), the local offset can be expressed as a function of the variable η2 as follows:

The DPWM mode can be achieved if the value of the parameter η2 in Eq. (27) is set to 1 or 0. We define iX = as the three-phase output currents, and i1 and i2 as the absolute values of the two currents, the respective phases of which can achieve the DPWM by setting the local offset voltage to e0MX and e0MN respectively. IMX and IMD are also defined as the maximum and medium absolute values of the three-phase currents, respectively. The selection rule of e0 for reduced switching loss can then be proposed as follows:

Applying the local offset defined in Eq. (28) allows only the output phases of maximum or medium absolute currents for DPWM control. This condition helps to avoid commutation on the phase of a large current, thus reducing the switching loss of the power converter.

C. Proposed PWM Control Scheme

The proposed PWM control scheme for multilevel NPC inverters under a DC voltage imbalance is described in Fig. 9 on the basis of the theoretical analysis. A global offset voltage is designed by using the information of the feedback DC-link-fed inverter voltages and the reference fundamental voltages. The reference switching voltages and the respective active and non-active components can be calculated afterwards. (VDX, eX) helps to determine the local offset limits and simplifies the PWM control of n-level to that of a virtual two-level inverter. The resultant switching sequences and switching time diagrams of the active voltages are directly derived from those of the two-level inverter PWM. The final PWM patterns of n-level NPC are completely realized using this information and in consideration of VLX.

Fig. 9.Proposed feed-forward PWM control scheme for n-level NPC inverter under DC voltage imbalance conditions.

 

IV. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

Simulations are conducted for a five-level NPC inverter with unbalanced DC-link voltages and a three-phase load R–L in series, where R = 40 Ω and L = 85 mH. The switching frequency is set to fs = 2kHz, and the output frequency is set to f0 = 50Hz. Under the conditions of V1 = 55V, V2 = 45V, V3 = 45V, AND V4 = 55V, two modulation indices of m = 0.3 and m = 0.75 are selected to analyze the typical conventional sinusoidal PWM method without compensation and with feed-forward compensation. For the uncompensated algorithm, the waveforms, including output line voltage and current (a) as well as the harmonic spectra of the current (b), are shown in Figs. 10 and 12. The obtained fundamental currents for the given loads are not correct, and the harmonic spectra in Figs. 10(b) and 12(b) show that the currents are influenced by low-order harmonics with a large magnitude. For comparison, the same quantities are given for the sinusoidal PWM method with feed-forward compensation, as in Figs. 11(a) (m = 0.3) and 13(a) (m = 0.75). Improvements are obtained when the compensated algorithm yields output waveforms in Figs. 11(a) and 13(a) with correct fundamental components and low-order harmonics, as depicted in Figs. 11(b) and 13(b). The obtained total harmonic distortion (THD) values of the output currents are 1.09% (m = 0.3) and 0.52% (m = 0.75), whereas they are 1.2% and 0.58% in the uncompensated system.

Fig. 10.(a) Output line voltage and current waveforms. (b) Harmonic spectrum of output currents (Fundamental = 0.63 A, THD = 1.2%) when using conventional sinusoidal PWM without feed-forward compensation (m = 0.3).

Fig. 11.(a) Output line voltage and current waveforms. (b) Harmonic spectrum of output currents (Fundamental = 0.7018 A, THD = 1.09%) when using conventional sinusoidal PWM with feed-forward compensation (m = 0.3).

Fig.12.(a) Output line voltage and current waveforms; (b) harmonic spectrum of output currents (Fundamental = 1.721 A, THD = 0.58%) when using conventional sinusoidal PWM without feed-forward compensation (m = 0.75).

Fig. 13.(a) Output line voltage and current waveforms; (b) harmonic spectrum of output currents (Fundamental = 1.79 A, THD = 0.52%) when using conventional sinusoidal PWM with feed-forward compensation (m = 0.75).

A medium CMV PWM method and a proposed PWM method with reduced switching loss are applied to a five-level NPC inverter with the previous configuration unchanged. The medium CMV PWM is achieved by using Equ. (17) and setting the local offset to zero. In the proposed PWM with reduced switching loss, the local offset is selected as the minimum CMV [Eq. (18)], and the local offset is selected as in Eq. (28).

The waveforms obtained using the two PWM methods are shown in Figs. 14 and 15. The resulting THDs of the output currents when using the feed-forward PWM with the medium CMV are 0.99%, 0.56%, and 0.38%, which correspond to modulation index m values of 0.3, 0.75, and 0.95, respectively. By contrast, the THDs are 1.46%, 0.66%, and 0.59% with the proposed PWM method with reduced switching loss.

Fig. 14.Output line voltage and current waveforms when using PWM method with medium CMV and feed-forward compensation.

Fig. 15.Waveforms of output line voltage and output pole voltage with its corresponding current when using the proposed feed-forward PWM method with reduced switching loss.

In the PWM with reduced switching loss, the waveforms of the pole voltage and its respective current for the three different modulation indices are illustrated in Fig. 15. No commutation on one phase occurs at some intervals of its maximum or medium absolute current. As a result of this proposed current-controlled DPWM mode, the switching loss can be significantly reduced, such as in the balanced input voltage case [25].

Figs. 16(a)–16(c) provide a detailed comparison of the line voltage THD when using the three feed-forward PWM control methods: the proposed PWM with reduced switching loss, the conventional sine PWM, and the medium CMV PWM. The THD is calculated up to the 100th harmonics of the output frequency. Each PWM method is analyzed to its maximum modulation index. For the sine PWM method, the maximum value of m is 0.866, whereas it is 1 for the other two methods. The DC-link voltages (V1,V2,V3,V4) for the THD analysis as in Figs. 16(a)–16(c) are set to (50 V, 50 V, 50 V, 50 V), (55 V, 45 V, 45 V, 55 V), and (45 V, 55 V, 55 V, 45 V), respectively.

Fig. 16.THD comparison of the three feed-forward PWM methods (fS = 5 kHz, R = 40Ω, L = 80 mH).

B. Experimental Results

Experimental hardware is built for the five-level NPC inverter to validate the proposed theory. The algorithm is implemented using the eZdsp TMS320F28335 control kit. Four DC voltages are measured with LEM LV25 NP Hall sensors. For the switching loss PWM algorithm, three additional Hall LEM LA25NP current sensors are used to measure the phase load currents. The frequency of the triangle carrier waveform is 2 kHz, and the desired output frequency is 50 Hz. The experimental load parameters are set to R = 40Ω and L = 85mH.

In the first experiment, two DC-link voltages V1,V4 are held constant, and the others have large ripples (Fig. 17). Each DC-link voltage of V1,V4 is created by a three-phase ull-wave diode bridge rectifier and a 6800 µ F capacitor. Two middle DC-link voltages V2,V3, each of which is created by one single-phase full-wave diode bridge rectifier and a 680 µ F capacitor, have a measured ripple in the range from 42 V to 60 V] when the inverter is in operation at the analyzed modulation index of 0.7.

Fig. 17.Setup of the DC-link fed inverter voltages (X: 10 ms/div; Y: 50 V/div).

The different capacitors produced different DC sources, which, in turn, caused asymmetrical output voltages. As shown in Fig. 18(a), without compensation, the distortion of the output current leads to significant low-order harmonics, as depicted in the harmonic spectrum in Fig. 18(b). The sinusoidal current is obtained as in Fig. 19(a) by using the compensated algorithm. The harmonic spectrum of the current in Fig. 19(b) also demonstrates a great reduction in low-order harmonics. The measured THD of the current with the compensated algorithm is 1.72%, whereas it is 2.725% in the uncompensated system.

Fig. 18.(a) Waveforms include output line voltage VAB, pole voltage VAO and current iA (X-axis:10 ms/div). (b) Harmonics spectrum of output current when using conventional sinusoidal PWM without feed-forward compensation (m = 0.7).

Fig. 19.(a) Waveforms including output line voltage VAB, pole voltage VAO, and current iA (X-axis:10 ms/div). (b) Harmonic spectrum of output current when using conventional sinusoidal PWM with feed-forward compensation (m = 0.7).

In the second experiment, the DC-link voltages are set to V1 = 55V, V2 = 45V, V3 = 45V, V4 = 55V. Figs. 20-22 depict the experimental waveforms of the output line voltage and the output current with its respective pole voltage when the feed-forward PWM methods of the sine PWM, the PWM with medium CMV, and the proposed DPWM are applied. The pole voltage waveform in Fig. 22 shows that similar to the simulation results, the implemented DPWM mode that depends on the phase load currents sets the non-commutation phase at intervals, in which its current attains the maximum or medium absolute value.

Fig. 20.Waveforms of output line voltage and pole voltage with its corresponding current when using sine PWM method with feed-forward compensation (X-axis:5ms/div).

Fig. 21.Waveforms of output line voltage and pole voltage with its corresponding current when using PWM method with medium CMV and feed-forward compensation (X-axis: 5 ms/div).

Fig. 22.Waveforms of output line voltage and pole voltage with its corresponding current when using feed-forward PWM method with reduced switching loss (X-axis: 5 ms/div).

A comparison of the experimental line voltage THD (calculated up to the 100th harmonics) of the proposed feed-forward DPWM method with the feed-forward sine PWM and medium CMV PWM is illustrated in Figs. 23(a)-23(c). modulation index. For the sine PWM method, the maximum value of m is 0.866, whereas it is 1 for the other two methods. The DC-link voltages (V1,V2,V3,V4) for the THD analysis as in Figs. 16(a)–16(c) are set to (50 V, 50 V, 50 V, 50 V), (55 V, 45 V, 45 V, 55 V), and (45 V, 55 V, 55 V, 45 V), respectively.

Fig. 23.Experimental THD comparison of the three feed-forward PWM methods (fS = 5 kHz, R = 40 Ω, L = 80 mH).

B. Experimental Results

Experimental hardware is built for the five-level NPC inverter to validate the proposed theory. The algorithm is implemented using the eZdsp TMS320F28335 control kit. Four DC voltages are measured with LEM LV25 NP Hall sensors. For the switching loss PWM algorithm, three additional Hall LEM LA25NP current sensors are used to measure the phase load currents. The frequency of the triangle carrier waveform is 2 kHz, and the desired output frequency is 50 Hz. The experimental load parameters are set to R = 40Ω and L = 85mH.

In the first experiment, two DC-link voltages V1,V4 are held constant, and the others have large ripples (Fig. 17). Each DC-link voltage of V1,V4 is created by a three-phase full-wave diode bridge rectifier and a 6800 µ F capacitor. Two middle DC-link voltages V2,V3, each of which is created by one single-phase full-wave diode bridge rectifier and a 680 µ F capacitor, have a measured ripple in the range from 42 V to 60 V] when the inverter is in operation at the analyzed modulation index of 0.7.

The different capacitors produced different DC sources, which, in turn, caused asymmetrical output voltages. As shown in Fig. 18(a), without compensation, the distortion of the output current leads to significant low-order harmonics, as depicted in the harmonic spectrum in Fig. 18(b). The sinusoidal current is obtained as in Fig. 19(a) by using the compensated algorithm. The harmonic spectrum of the current in Fig. 19(b) also demonstrates a great reduction in low-order harmonics. The measured THD of the current with the compensated algorithm is 1.72%, whereas it is 2.725% in the uncompensated system.

In the second experiment, the DC-link voltages are set to V1 = 55V, V2 = 45V, V3 = 45V, V4 = 55V. Figs. 20-22 depict the experimental waveforms of the output line voltage and the output current with its respective pole voltage when the feed-forward PWM methods of the sine PWM, the PWM with medium CMV, and the proposed DPWM are applied. The pole voltage waveform in Fig. 22 shows that similar to the simulation results, the implemented DPWM mode that depends on the phase load currents sets the non-commutation phase at intervals, in which its current attains the maximum or medium absolute value.

A comparison of the experimental line voltage THD (calculated up to the 100th harmonics) of the proposed feed-forward DPWM method with the feed-forward sine PWM and medium CMV PWM is illustrated in Figs. 23(a)-23(c).

The characteristics of the line voltage THD using the three PWM methods under the same conditions of DC voltages as in Figs. 16(a)–16(c) yield acceptable results in comparison with those obtained by simulation (Fig. 16). The experimental THD characteristics indicate that the proposed DPWM method under three given DC-link voltage conditions yield higher THD values than the two other PWM methods in nearly the entire region of the modulation index.

 

V. CONCLUSIONS

In this study, a model of switching voltages and an offset-based PWM scheme for multilevel NPC inverters under a DC voltage imbalance are proposed. In the proposed scheme, the global offset extends the maximized output voltage range in the under-modulation range and defines a draft CMV. The local offset can be flexibly modified to establish different PWM modes related to the PWM quality, such as switching loss and current ripple. A DPWM that utilizes these flexible offsets and the feedback information of the currents is proposed to reduce switching loss. The proposed PWM for switching loss reduction can be analyzed in relation to other carrier-based methods using the same switching voltage model. Simulations and experiments are conducted to confirm the validity of the proposed switching voltage modeling and the proposed DPWM control method.