• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1045-1054
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• 2006

In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.15-21
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• 2008

Several shared buses are divided hierarchically and connected with a bridge in the bus topology that consists of many components such as SoCs. Because the bridge topology is capable of the simultaneous communication of components in the several buses, the bus performance has improved definitely. However, when the inter-bus data transaction happens, the latency increases seriously in the bridge block. In this paper, a variety of bridge architectures are analyzed in the point of view of merit and demerit. Superior frying bridge topology is proposed in the aspects of performance, IP reusability, timing margin, gate count and circuit complexity. In contrast with the conventional bridge that has only a role to switch the inter-bus data, the frying bridge can communicate directly between the bus and the slave, which decreases the traffic overhead of a shared bus and improves the performance of a bridge communication.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.646-647
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• 2007

The topology processor uses the status of circuit breakers as input. It operates on the bus section connectivity data, which is stored in the data base, to determine the bus/branch topology of the network. This output of the topology processor forms part of the input to the state estimation or dispatcher power flow. This paper describes the development of the topology processor using matrix structure.

• ETRI Journal
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• v.32 no.5
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• pp.713-721
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• 2010

E-textile technology has earned a great deal of interest in many fields; however, existing wearable network protocols are not optimized for use with conductive yarn. In this paper, some of the basic properties of conductive textiles and requirements on wearable personal area networks (PANs) are reviewed. Then, we present a wearable personal network (WPN), which is a four-layered wearable PAN using bus topology. We have designed the WPN to be a lightweight protocol to work with a variety of microcontrollers. The profile layer is provided to make the application development process easy. The data link layer exchanges frames in a master-slave manner in either the reliable or best-effort mode. The lower part of the data link layer and the physical layer of WPN are made of a fabric serial-bus interface which is capable of measuring bus signal properties and adapting to medium variation. After a formal verification of operation and performances of WPN, we implemented WPN communication modules (WCMs) on small flexible printed circuit boards. In order to demonstrate the behavior of our WPN on a textile, we designed a WPN tutorial shirt prototype using implemented WCMs and conductive yarn.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.6
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• pp.259-265
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• 2000

The purpose of this paper is to detect and identify topological errors in order to maintain a reliable database for the state estimator. In this paper, a two stage estimation procedure is used to identify the topology errors. At the first stage, the WSAV state estimator which has characteristics to remove bad data during the estimation procedure is run for finding out the suspected branches at which topology errors take place. The resulting residuals are normalized and the measurements with significant normalized residuals are selected. A set of suspected branches is formed based on these selected measurements; if the selected measurement is a line flow, the corresponding branch is suspected; if it is an injection, then all the branches connecting the injection bus to its immediate neighbors are suspected. A new WLAV state estimator adding the branch flow errors in the state vector is developed to identify the branch topology errors. Sample cases of single topology error and topology error with a measurement error are applied to IEEE 14 bus test system.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.21-22
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• 2007

Topology processing is indispensable basic function as it generate a real-time BUS-BRANCH model in Energy Management Systems because most application softwares such as state estimation, power flow, etc., require BUS-BRANCH circuit data. This paper propose an expert system to generate BUS-BRANCH circuit model using Artificial Intelligence technology and it is applied to 154kV distribution substations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.88-96
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• 2015

This paper describes a new method for enhancing the accuracy of network analysis applications in energy management systems. Topology processing, state estimation, power flow analysis, and contingency analysis play a key factor in the stable and reliable operation of power systems. In this respect, the aim of topology processing is to provide the electrical buses and the electrical islands with the actual state of the power system as input data. The results of topology processing is used to input of other applications. New method, which includes the topology error analysis based on inconsistency check, coherency check, bus mismatch check, and outaged device check is proposed to enhance the accuracy of network analysis. The proposed methodology is conducted by energy management systems and the Korean power systems have been utilized for the test systems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.8
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• pp.1053-1058
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• 2013

Because of computational burden and complex topology of substation, a transmission overload relief using circuit-breaker switching was very complex and difficult. However, a on-line algorithm for reducing the overloads in transmission lines has made progress due to the advance of IT technology. This paper describes the methodology for alleviating the overloads in transmission lines by circuit-breaker switching. First, the severe contingency lists and substations were selected from the results of contingency analysis. Then the switch combinations are determined using circuit-breakers of the selected substation. The topology changes are limited to equipment outage, bus split, island split, bus merge and island merge. Finally, the fast screening and full analysis methods are used to analyze the overload in transmission lines. To verify the performance of the proposed methodology, we performed a comprehensive test for both test system and large-scale power systems. The results of these tests showed that the proposed methodology can accurately alleviate the overloads in transmission lines from online data and can be applied to on-line applications.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.27-29
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• 2004

This paper presents improved teaching and learning Gill for easily analysis tool of load flow of power system. This GUI includes not only contingency analysis function, but also calculating power loss from transmission line flow. The Gill is friendly for study for power system operation and control because picture provide a better visualizing of relationships between input parameters and effect than a tabula type result. This Gill enables topology and the output data of load flow for line outages to be shown on same picture page. Users can input the system data for power flow on the the picture and can easily see the the result diagram of bus voltage, bus power, line flow. It is also observe the effects of different types of variation of tap, shunt capacitor, loads level, line outages. Proposed Gill has been studied on the Ward-Hale 6-Bus system.