• Title/Summary/Keyword: data Parallel

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Design of ramp-stress accelerated life test plans for a parallel system with two independent components using masked data

  • Srivastava, P.W.;Savita, Savita
    • International Journal of Reliability and Applications
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    • v.18 no.2
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    • pp.45-63
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    • 2017
  • In this paper, we have formulated optimum Accelerated Life Test (ALT) plan for a parallel system with two independent components using masked data with ramp-stress loading scheme and Type-I censoring. Consider a system of two independent and non-identical components connected in parallel. Such a system fails whenever all of its components has failed. The exact component that causes the system to fail is often unknown due to cost and time constraint. For each parallel system at test, we observe its system's failure time and a set of component that includes the component actually causing the system to fail. The stress-life relationship is modelled using inverse power law, and cumulative exposure model is assumed to model the effect of changing stress. The optimal plan consists in finding out the optimum stress rate using D-optimality criterion. The method developed has been explained using a numerical example and sensitivity analysis carried out.

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A New Prediction-Based Parallel Event-Driven Logic Simulation (새로운 예측기반 병렬 이벤트구동 로직 시뮬레이션)

  • Yang, Seiyang
    • KIPS Transactions on Computer and Communication Systems
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    • v.4 no.3
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    • pp.85-90
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    • 2015
  • In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

Parallel Driven Power Supply with Low Cost Hot Swap Controller for Server (저가형 Hot Swap Controller를 가지는 병렬 구동 서버용 전원 장치)

  • Yi, KangHyun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.6
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    • pp.738-744
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    • 2018
  • This paper proposes a low cost hot swap operation circuit of a parallel operation power supply for servers. Hot swap function for server power system is essential in 24 hour operation system such as internet data center, server, factory and etc. Server power supplies used in internet data centers have two or more parallel operations with the hot swap operation. However, the cost of the power supply is high because the controller IC for hot swap operation is very expensive. Therefore, this paper proposes a parallel-operated power supply with a low-cost hot swap controller for servers. The proposed system can operate hot swap function by using discrete devices and reduce the cost by more than 50%. A 1.2kW prototype system is implemented to verify the proposed low cost hot swap controller.

Parallel and Sequential Implementation to Minimize the Time for Data Transmission Using Steiner Trees

  • Anand, V.;Sairam, N.
    • Journal of Information Processing Systems
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    • v.13 no.1
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    • pp.104-113
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    • 2017
  • In this paper, we present an approach to transmit data from the source to the destination through a minimal path (least-cost path) in a computer network of n nodes. The motivation behind our approach is to address the problem of finding a minimal path between the source and destination. From the work we have studied, we found that a Steiner tree with bounded Steiner vertices offers a good solution. A novel algorithm to construct a Steiner tree with vertices and bounded Steiner vertices is proposed in this paper. The algorithm finds a path from each source to each destination at a minimum cost and minimum number of Steiner vertices. We propose both the sequential and parallel versions. We also conducted a comparative study of sequential and parallel versions based on time complexity, which proved that parallel implementation is more efficient than sequential.

A Design and Implementation of Parallel Programming Environment using Graphical User Interface (그래픽 사용자 인터페이스를 이용한 병렬 프로그래밍 환경 설계 및 구현)

  • 이원용;박두순
    • Journal of Korea Multimedia Society
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    • v.4 no.6
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    • pp.579-587
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    • 2001
  • In this paper, we design and implement a parallel programming environment using graphicial user interface. Parallel program must be written according to the characters of various hardwares or programs. So it is difficult to write the parallel program. In this paper, we design and implement a parallel programming environment which solved this problem. The traditional parallel compiler provides the parallel information in the text environment. But this paper provides the parallel information using graphicial user interface so that the user may use it more easily. This parallel environment provide functions such as, data dependence analysis, CFG, HTF, and loop transformation.

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A Parallel Emulation Scheme for Data-Flow Architecture on Loosely Coupled Multiprocessor Systems (이완 결합형 다중 프로세서 시스템을 사용한 데이터 플로우 컴퓨터 구조의 병렬 에뮬레이션에 관 한 연구)

  • 이용두;채수환
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.12
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    • pp.1902-1918
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    • 1993
  • Parallel architecture based on the von Neumann computation model has a limitation as a massively parallel architecture due to its inherent drawback of architectural features. The data-flow model of computation has a high programmability in software perspective and high scalability in hardware perspective. However, the practical programming and experimentaion of date-flow architectures are hardly available due to the absence of practical data-flow, we present a programming environment for performing the data-flow computation on conventional parallel machines in general, loosely compled multiprocessor system in particular. We build an emulator for tagged token data-flow architecture on the iPSC/2 hypercube, a loosely coupled multiprocessor system. The emulator is a shallow layer of software executing on an iPSC/2 system, and thus makes the iPSC/2 system work as a data-flow architecture from the programmer`s viewpoint. We implement various numerical and non-numerical algorithm in a data-flow assembler language, and then compare the performance of the program with those of the versions of conventional C language, Consequently, We verify the effectiveness of this programming environment based on the emulator in experimenting the data-flow computation on a conventional parallel machine.

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A Study on the Performance Improvement of Machine Translation Using Public Korean-English Parallel Corpus (공공 한영 병렬 말뭉치를 이용한 기계번역 성능 향상 연구)

  • Park, Chanjun;Lim, Heuiseok
    • Journal of Digital Convergence
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    • v.18 no.6
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    • pp.271-277
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    • 2020
  • Machine translation refers to software that translates a source language into a target language, and has been actively researching Neural Machine Translation through rule-based and statistical-based machine translation. One of the important factors in the Neural Machine Translation is to extract high quality parallel corpus, which has not been easy to find high quality parallel corpus of Korean language pairs. Recently, the AI HUB of the National Information Society Agency(NIA) unveiled a high-quality 1.6 million sentences Korean-English parallel corpus. This paper attempts to verify the quality of each data through performance comparison with the data published by AI Hub and OpenSubtitles, the most popular Korean-English parallel corpus. As test data, objectivity was secured by using test set published by IWSLT, official test set for Korean-English machine translation. Experimental results show better performance than the existing papers tested with the same test set, and this shows the importance of high quality data.

Reliability Estimation in Bivariate Pareto Model with Bivariate Type I Censored Data

  • Cho, Jang-Sik;Cho, Kil-Ho;Kang, Sang-Gil
    • Journal of the Korean Data and Information Science Society
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    • v.14 no.4
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    • pp.837-844
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    • 2003
  • In this paper, we obtain the estimator of system reliability for the bivariate Pareto model with bivariate type 1 censored data. We obtain the estimators and approximated confidence intervals of the reliability for the parallel system based on likelihood function and the relative frequency, respectively. Also we present a numerical example by giving a data set which is generated by computer.

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Interprocedural Transformations for Parallel Computing

  • Park, Doo-Soon;Choi, Min-Hyung
    • Journal of Korea Multimedia Society
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    • v.9 no.12
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    • pp.1700-1708
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    • 2006
  • Since the most program execution time is consumed in a loop structure, extracting parallelism from loop programs is critical for the taster program execution. In this paper, we proposed data dependency removal method for a single loop. The data dependency removal method can be applied to uniform and non-uniform data dependency distance in the single loop. Procedure calls parallelisms with only a single loop structure or procedure call most of other methods are concerned with the uniform code within the uniform data dependency distance. We also propose an algorithm, which can be applied to uniform, non-uniform, and complex data dependency distance among the multiple procedures. We compared our method with conventional methods using CRAY-T3E for the performance evaluation. The results show that the proposed algorithm is effective.

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