• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Honam Mathematical Journal
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• v.29 no.3
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• pp.415-425
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• 2007

The normal basis has the advantage that the result of squaring an element is simply the right cyclic shift of its coordinates in hardware implementation over finite fields. In particular, the optimal normal basis is the most efficient to hardware implementation over finite fields. In this paper, we propose an efficient parallel architecture which transforms the Gaussian normal basis multiplication in GF($2^m$) into the type-I optimal normal basis multiplication in GF($2^{mk}$), which is based on the palindromic representation of polynomials.

• Journal of the Earthquake Engineering Society of Korea
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• v.12 no.6
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• pp.65-71
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• 2008

A one-dimensional site response analysis program (KODSAP) was developed using cyclic soil behavior model by using the modified parallel IWAN model. The model is able to predict the cyclic hardening and degradation of soil through the adjustment of the internal slip stresses of its elements beyond the cyclic threshold, and satisfies Bauschinger's effect and the Masing rule in terms of its own behavior characteristics. The program (KODSAP) used the direct integration method in the time domain. The elasticity of the base rock was considered as a viscous damper boundary condition. The effects of cyclic hardening or degradation of soil on site response analysis were evaluated through parametric studies. Three types of analyses were performed to compare the effect of analysis and cyclic parameter on site response. The first type was equivalent linear analysis, the second was nonlinear analysis, and a third was nonlinear analysis using the cyclic hardening or degradation model.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.36-42
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• 2010

This paper presents a hybrid approach to the construction of quasi-cyclic (QC) low-density parity-check (LDPC) codes based on parallel bundles in Euclidean geometries and circulant permutation matrices. Codes constructed by this method are shown to be regular with large girth and low density. Simulation results show that these codes perform very well with iterative decoding and achieve reasonably large coding gains over uncoded system.

• Bulletin of the Korean Mathematical Society
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• v.55 no.1
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• pp.227-237
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• 2018

In this paper, we study some geometric structures of a weakly cyclic Z-symmetric manifold (briefly, $[W CZS]_n$). More precisely, we prove that a conformally flat $[W CZS]_n$ satisfying certain conditions is special conformally flat and hence the manifold can be isometrically immersed in an Euclidean manifold $E^n+1$ as a hypersurface if the manifold is simply connected. Also we show that there exists a $[W CZS]_4$ with one parameter family of its associated 1-forms.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1655-1662
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• 1993

In this paper we discuss three algorithms-Direct, Successive, and Recursive-on parallel CRC(Cyclic Redundancy Check) verification. The algorithms are derived by combining the byte-syndromes precomputed from the generator polynomial. These algorithms are compared in terms of the amount of hardware and the speed of operation. Since the algorithms can be generalized easily, we took the ATM cell delineation example for easier description. As an application of the algorithm Recursive, an ATM cell delineation module suitable for STM-1 transmission has been successfully realized through commercially available field programmable gate arrays.