• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• ETRI Journal
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• v.10 no.3
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• pp.49-61
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• 1988

HARP(High-performance Architecture for Risc-type Processor)는 한국전자통신연구소에서 정의한 고유모델의 RISC형 32비트 CPU이다. HACAM(HArp CAche and Mmu)은 HARP의 캐쉬 메모리 및 MMU(Memory Management Unit)를 custom IC로 구현한 VLSI 칩이다. 본 논문에서는 HACAM의 구조 설계에 대해 메모리 구조 및 메모리 관리 방식, 캐쉬 메모리 및 HACAM의 구성 등으로 나누어 설명하고 그 타당성을 논하였다.

• Journal of IKEEE
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• v.22 no.1
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• pp.87-92
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• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• Journal of KIISE
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• v.42 no.10
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• pp.1280-1285
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• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.39-47
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• 1997

This paper presents a single board digital signal processing system which can perform two-dimensional (2-D) digital infinite impulse response (IIR) filtering in realtime. We have developed an architecture to provide not only the necessary computational power but also a balance of the system input/output and computational requirements. The architecture achieves large system throughput by using highly parallel processing at both the system and processor levels. It reduces system data communication requirements significantly by taking advantage of a custom-designed processor and by providing each processor with its own input and ouput channel. After system initialization, almost 100 percent of the time is used for data processing. Data transfers occur concurrently with data processing. The functional level simulation reveals that the system throughput can reach as high as one pixel per system cycle. With only 10MHz clock frequency system, it can implement up to fourth order 2-D IIR filters for video-rate data ($512\times512$ pixels per frame at 30 frames per second). If we increase the system frequency, the system can be used for the preprocessing and postprocessing of video signal of HDTV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}