• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• Journal of Information Display
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• 제9권3호
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• pp.1-7
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• 2008

With the aim of creating a high-quality display system with value-added functions, we designed a current mode multiplexer for LTPS TFT devices. The multiplexers had less than 1 volt logic swing, and speed improvement was evident compared with that of conventional CMOS architecture. We refined the multiplexer to achieve a more stable current steering operation. By using the versatility of the multiplexer, a new NAND/AND and NOR/OR logic gates were designed through the simple modification of signal connections. Two micron LTPS TFT parameters were used during the HSPICE simulation of the circuits.

• Journal of Advanced Marine Engineering and Technology
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• 제21권4호
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• pp.387-392
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• 1997

This paper describes a combination surge generator for carrying out performance tests on the surge protection circuits of shipboard electrical systems. Pspice simulations were performed to decide the values of the parts required and to analyze the characteristics of the generator circuitry. The surge generator fabricated can produce four of the most common surge test waveforms : the O.5i/S/100kHz Ringwave, the 1.2/50$\mu$S voltage, the 8/20$\mu$S current, and the lO/lOOOi/S voltage wave¬forms specified in ANSI Std. C62. Source impedances of the surge generator are 12$\Omega$ in the O.5$\mu$S/100kHz mode, O.5$\Omega$ in the 1.2/50$\mu$S and 8/20$\mu$S mode, and 40$\Omega$in the l0/1000$\mu$S mode, and are determined by the ratio of the maxi¬mum open - circuit voltage to the maximum short - circuit current. Experimental results show that the surge generator provides most of the outputs required for the testing of the surge protection circuits on shipboard electrical systems.

• 한국정보통신학회논문지
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• 제2권3호
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• pp.439-446
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• 1998

본 논문에서는 다치 논리를 기본으로 한 SD 가산기 및 PD 가산기를 설계하였다. 전류 모드 CMOS 회로를 이용하여 다치 논리를 구현하였으며 부분곱으로 전압모드 CMOS 회로도 이용하였다. 설계된 회로에 대한 검증은 대부분 SPICE 시뮬레이션을 통해 확인하였다. 다치 부호를 적용한 SD(Signed-Digit) 수 표현을 사용하여 자리 올림 신호의 전송이 자리수에 관계없이 1단에서 실행되게 함으로써 병렬연산의 고속화를 가능하게 하였고, 또한 M개의 다 입력을 처리하는 가산기에서는 적당한 PD(Positive-digit) 수 표현을 사용하여 가산의 단수를 줄일 수 있으므로 연산의 고속화 및 고집적화를 가능하게 하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• 한국산학기술학회논문지
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• 제10권12호
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• pp.3614-3621
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• 2009

본 논문에서는 이득 및 주파수 특성이 개선된 CMOS 저전압 전류모드 적분기가 설계되었다. 설계된 전류모드 적분기는 본 논문에서 새롭게 제안한 선형 캐스코드 회로를 기본으로 구성되었다. 제안된 전류모드 적분기는 기존의 전류미러형 전류모드 적분기의 이득(43.7dB) 및 단위이득주파수(15.2MHz) 비해서 높은 전류이득(47.8dB) 및 단위 이득 주파수(27.8MHz)의 특성을 얻을 수 있었다. 제안된 전류모드 적분기의 응용회로로써 차단주파수 7.03MHz를 갖는 5차 체비세프 저역통과 필터를 설계하였다. 설계된 모든 회로들은 1.8V-$0.18{\mu}m$ CMOS 공정파라메터로써 HSPICE를 이용하여 시뮬레이션되었다.

• International Journal of Aerospace System Engineering
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• 제9권1호
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• pp.1-15
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• 2022

Pyrotechnic initiators provide a source of pyrotechnic energy used to initiate a variety of space mechanisms. Pyrotechnic systems build in electromagnetic environment that may lead to critical or catastrophic hazards. Special precautions are need to prevent a pulse large enough to trigger the initiator from appearing in the pyrotechnic firing circuits at any but the desired time. The EMC verification shall be shown by analysis or test that the pyrotechnic systems meets the requirements of inadvertent activation. The MIL-STD-1576 and two range safeties, AFSPC and CSG, require the safety margin for electromagnetic potential hazards to pyrotechnic systems to a level at least 20 dB below the maximum no-fire power of the EED. The PC23 is equivalent to NASA standard initiator and the 1EPWH100 squib is ESA standard initiator. This paper verifies the two safety margins for electromagnetic potential hazards. The first is verified by analyzing against a RF power. The second is verified by testing against a DC current. The EMC safety margin requirement against RF power has been demonstrated through the electric field coupling analysis in differential mode with 21 dB both PC23 and 1EPWH100, and in common mode with 58 dB for PC23 and 48 dB for 1EPWH100 against the maximum no-fire power of the EED. Also, the EMC safety margin requirement against DC current has been demonstrated through the electrical isolation test for the pyrotechnic firing circuits with greater than 20 dB below the maximum no-fire current of the EED.

• 한국통신학회논문지
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• 제21권4호
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• pp.1068-1076
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• 1996

저전압 아날로그 전류모드 능동필터의 기본블럭으로 응용될 수 있는 새로운 구조를 갖는 연속시간 전류모드 적분기를 제안한다. 제안된 전류모드 적분기를 Zele등이 설계한 기존 전류모드 적분기와 비교하여, 단위이득 주파수, 부하구동능력 및 소비전력이 개선될 수 있음을 소신호 해석 및 시뮬레이션을 통하여 입증하였다. 제안된 전류 모드 적분기를 이용하여 전류모드 3차 저역 능동필터를 설계하고, 설계된 능동필터를 ORBIT사의 $1.2{\mu}{\textrm{m}}$ double-poly double-metal CMOS n-well 공정을 이용하여 칩으로 제작하였다. 제작된 전류모드 능동필터의 측정결과, 단일 3.3V의 공급전압을 인가시 44.5MHz의 -3dB 차단주파수와 3.3mW의 소비전력 특성을 나타내었으며, 필터의 전체 칩면적은 $0.12mm^2$ 였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.