• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.465-470
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• 2010

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Transactions of the Korean Society of Automotive Engineers
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• v.19 no.2
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• pp.105-110
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• 2011

Through this study, the performance evaluation on the addition of low-pressure loop EGR(Exhaust Gas Recirculation) in a 6.0 L commercial diesel engine was carried out using WAVE modeling and simulation. Since the key technology of advanced diesel engine combustion such as low-temperature combustion is to steadily supply high rates of EGR in a wide operating range, the current study could be effectively contribute to the design and development processes of up-to-date diesel engine systems as real-world reference data. The current simulation results show that the system in which low-pressure loop EGR is added shows almost 2.3 times increase in maximum EGR rate at 1000 rpm as well as almost 1.6 times increase at 2200 and 1600 rpm in comparison with an engine system employing high-pressure loop EGR only. Also, both turbocharger axis speed and charging pressure level did not deteriorate due to the addition of low-pressure loop EGR at 2200 and 1000 rpm, but they were fairly decreased at 1600 rpm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of Korean Society of Transportation
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• v.12 no.4
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• pp.35-52
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• 1994

In order to operate the computerized traffic signal system, it requires the detectors which ensure the exact detections of actual traffic data (e.g., traffic volume, occupancy and velocity of vehicles). The octagonal detectors are used currently in Korea. However, the maintenance of the detectors has many problems with the road repairs and the constructions on the pavement, and failure due to the disconnection of the wires. Serious delay due to the long installation time of loops also causes the traffic disturbances. The low sensitivities and splash-over effect can sometimes create error data after installation of the octagonal loops. The mai purpose of this study is to evaluate the feasibility of domestic use of the round (circular) inductive loops which developed recently in U.S.A. It was found that the round loops are comparable to the existing octagonal loops. In addition, the use of the high quality of materials in the round loop system can reduce the current problems and weakpoints of the octagonal loops. The installation cost of the round loop was found out as economic as the octagonal loop. The installation time of the round loop system can be reduced with the specially equipped loop truck, and wide/deep slots without sharp corners can extend the durability without serious stress of loop head wires. In conclusion, the round loop is superior to the octagonal type in overall points. It is recommended that the localization of the materials and equipments of round loop system is required to carry out the extensive local installations. Also, several contractors to meet the nationwide demand should be arranged to gurantee the proper maintenance and operation of the systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of Power Electronics
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• v.7 no.3
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• pp.265-270
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• 2007

Equal rating DC-DC converter modules can be connected in series at the input for circuits requiring higher input voltages and in parallel at the output for circuits requiring higher output currents. Since the converter modules may not be practically identical, closed loop control has to ensure that each module equally shares the total input voltage and the load current. A control scheme consisting of a common output voltage loop, individual inner current loops and individual input voltage loops have been designed in this work to achieve input voltage and load current sharing as well as load voltage regulation under supply and load disturbances. The output voltage loop provides the basic reference for the inner current loops, which are also modified by the respective input voltage loops. The average of the converter input voltages, which is dynamically varying, is chosen as the reference for input voltage loops. This choice of reference eliminates interaction among different control loops. Type II compensators and Fuzzy Logic Controllers (FLCs) are designed and compared through MATLAB based simulation and FLC is found to be satisfactory. Hence TMS320F2407A DSP based FLC is implemented and the results are presented which prove the superiority of the FLC developed for this research.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.260-265
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• 1999

This paper describes a novel control method of a three-phase PWM inverter for uninterruptible power supply(UPS) applications. To obtain the fast dynamics and excellent harmonic characteristics, a new state feedback control technique is proposed. The proposed control consists of the inner-loop current and outer-loop voltage controllers with a load current estimator to reduce the effects of the load variations and nonlinearity. In order to verify the effectiveness of the proposed control, the simulation is carried out for various load condition.

• 한국전산유체공학회:학술대회논문집
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• 1995.10a
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• pp.132-137
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• 1995

Numerical analysis is conducted on the deformation of free surface of magnetic fluid. Steady magnetic fields are induced by a circular current loop. Governing equations of magnetic fields are solved by using the concept of vector potential. The free surface of magnetic fluid is formed by the balance of surface force, gravity, pressure difference, magnetic normal pressure and magnetic body force. The deformations of free surface of magnetic fluid are qualitatively clarified. And, the patterns of steady non-uniform magnetic fields induced by a circular current loop are quantitatively presented.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1209-1211
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• 2001

Generally, the current controller is located inner the whole controller, so the characteristic of the current controller is important in controlling performance of the upper controller. A current control loop in motor control is designed so that it is 10 times faster than the speed control loop of the upper controller. Thus, the current controller with complex control algorithm is not proper. In this paper, the improved current controller using a conventional digital PI controller and feedforward controller for the brushless BC motor is designed.