• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1333-1336
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• 1998

Hydrogenated amorphous silicon(a-Si:H) films which were deposited by plasma enhanced chemical deposition(PECVD) have been recrystallized by the two-step rapid thermal annealing(RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallzation step. In result, the recrystallized polycrystalline silicon(poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on the silicon wafers. The maximun ON/OFF current ratio of the device was over $10^5$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.

• 한국결정성장학회지
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• 제8권1호
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• pp.55-63
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• 1998

조성이 각각 1.9 $SiO_2-1.5\;Na_2O-Al_2O_3-40\;H_2O$인 반응물과 10 $SiO_2-7\;Na_2O-Al_2O_3-280\;H_2O$인 반응물로부터 다공성 지지판에 성장된 A형 및 Y형 제올라이트 결정박막을 합성하였다. 합성된 제올라이트 막은 X선회절분석기와 주사전자현미경으로 특성을 검토하였다. 지지체 상에 붙어 성장한 A 및 Y형 제올라이트 결정은 치밀하게 서로 붙은 상태였으며 그 두께가 약 8-15$\mu$m 정도였다. 또한 반응물을 조제할 때, 물은 첨가하지 않은 채로 혼합하고 디스크형으로 가압성형하여 $100^{\circ}C$에서 결정화시켜도 치밀하게 성장된 제올라이트 결정박막을 합성할 수 있었다. 박막으로 결정화시킨 A형 제올라이트는 미세세공의 분자체기능을 통하여 물과 메탄올의 혼합수용액에서 물만을 선택적으로 투과시키는 것을 알 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 춘계종합학술대회
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• pp.403-406
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• 1999

고상결정화(SPC)로 제작된 다결정 박막의 전기적 특성 변화를 측정함으로서 다결정 박막 트랜지스터(poly-Si TFT's)에 대한 온도 변화 (25～1$25^{\circ}C$)의 영향을 연구하였다. 채널 길이가 각각 1.5, 10 $\mu\textrm{m}$인 SPC로 제작된 n-채널 poly-Si TFT는 온도 변화에도 불구하고 높은 전계 효과 이동도 ($\mu$$_{FE}$ : 1.5와 10$\mu\textrm{m}$에서 각각 $\geq$82 and $\geq$60$\textrm{cm}^2$/V-s), 낮은 문턱전압 (V$_{th}$ : 1.5 와 10$\mu\textrm{m}$에서 각각 $\leq$ 1.52 and $\leq$ 2.75V), 낮은 Subthreshold swing (S$_{t}$), 그리고 양호한 ON-OFF 특성이 나타났다. 따라서, SPC로 제작된 poly-Si TFT는 액정표시장치의 주변회로에 적용할 수 있다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.154-155
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• 2012

The promise of nano-crystalites (nc) as a technological material, for applications including display backplane, and solar cells, may ultimately depend on tailoring their behavior through doping and crystallinity. Impurities can strongly modify electronic and optical properties of bulk and nc semiconductors. Highly doped dopant also effect structural properties (both grain size, crystal fraction) of nc-Si thin film. As discussed in several literatures, P atoms or radicals have the tendency to reside on the surface of nc. The P-radical segregation on the nano-grain surfaces that called self-purification may reduce the possibility of new nucleation because of the five-coordination of P. In addition, the P doping levels of ${\sim}2{\times}10^{21}\;at/cm^3$ is the solubility limitation of P in Si; the solubility of nc thin film should be smaller. Therefore, the non-activated P tends to segregate on the grain boundaries and the surface of nc. These mechanisms could prevent new nucleation on the existing grain surface. Therefore, most researches shown that highly doped nc-thin film by using conventional PECVD deposition system tended to have low crystallinity, where the formation energy of nucleation should be higher than the nc surface in the intrinsic materials. If the deposition technology that can make highly doped and simultaneously highly crystallized nc at low temperature, it can lead processes of next generation flexible devices. Recently, we are developing a novel CVD technology with a neutral particle beam (NPB) source, named as neutral beam assisted CVD (NBaCVD), which controls the energy of incident neutral particles in the range of 1~300eV in order to enhance the atomic activation and crystalline of thin films at low temperatures. During the formation of the nc-/pm-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. In the case of phosphorous doped Si thin films, the doping efficiency also increased as increasing the reflector bias (i.e. increasing NPB energy). At 330V of reflector bias, activation energy of the doped nc-Si thin film reduced as low as 0.001 eV. This means dopants are fully occupied as substitutional site, even though the Si thin film has nano-sized grain structure. And activated dopant concentration is recorded as high as up to 1020 #/$cm^3$ at very low process temperature (＜ $80^{\circ}C$) process without any post annealing. Theoretical solubility for the higher dopant concentration in Si thin film for order of 1020 #/$cm^3$ can be done only high temperature process or post annealing over $650^{\circ}C$. In general, as decreasing the grain size, the dopant binding energy increases as ratio of 1 of diameter of grain and the dopant hardly be activated. The highly doped nc-Si thin film by low-temperature NBaCVD process had smaller average grain size under 10 nm (measured by GIWAXS, GISAXS and TEM analysis), but achieved very higher activation of phosphorous dopant; NB energy sufficiently transports its energy to doping and crystallization even though without supplying additional thermal energy. TEM image shows that incubation layer does not formed between nc-Si film and SiO2 under later and highly crystallized nc-Si film is constructed with uniformly distributed nano-grains in polymorphous tissues. The nucleation should be start at the first layer on the SiO2 later, but it hardly growth to be cone-shaped micro-size grains. The nc-grain evenly embedded pm-Si thin film can be formatted by competition of the nucleation and the crystal growing, which depend on the NPB energies. In the evaluation of the light soaking degradation of photoconductivity, while conventional intrinsic and n-type doped a-Si thin films appeared typical degradation of photoconductivity, all of the nc-Si thin films processed by the NBaCVD show only a few % of degradation of it. From FTIR and RAMAN spectra, the energetic hydrogen NB atoms passivate nano-grain boundaries during the NBaCVD process because of the high diffusivity and chemical potential of hydrogen atoms.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.281-281
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• 2007

Low Temperature Co-fired Ceramic (LTCC) technology has been used in electronic device for various functions. LTCC technology is to fire dielectric ceramic and a conductive electrode such as Ag or Cu thick film below the temperature of $900^{\circ}C$ simultaneously. The glass-ceramic has been widely used for LTCC materials due to its low sintering temperature, high mechanical properties and low dielectric constants. To obtain the high strength, addition of filler, the microstructure should have various crystals and low pores in a composite. In this study, two glass frits were mixed with different alumina size(0.5, 2, 3.7um) and sintered at the range of $850{\sim}950^{\circ}C$. The microstructure, crystal phases, thermal and mechanical properties of the composites were investigated using FE-SEM, XRD, TG-DTA, Dilatomer. When the particle size of $Al_2O_3$ filler increased, the starting temperatures for the densification of the sintered bodies, onset point of crystallization, peak crystallization temperature in the glass-ceramic composites decreased gradually. After sintered at $900^{\circ}C$, the glass frits were crystallized as $CaAl_2Si_2O_8\;and\;CaMgSi_2O_6$. The purpose of our study is to understand the relationship between the $Al_2O_3$ particle size and thermal properties in composites.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.281-284
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• 2007

Recently, we have developed p-i-n a-Si:H single junction thin film solar cells with RF (13.56MHz) plasma enhanced chemical vapor deposition (PECVD) system, and also successfully fabricated the mini modules ($>300cm^2$), using the laser patterning technique to form an integrated series connection. The efficiency of a mini module was 7.4% ($Area=305cm^2$, Isc=0.25A, Voc=14.74V, FF=62%). To fabricate large area modules, it is important to optimise the integrated series connection, without damaging the cell. We have newly installed the laser patterning equipment that consists of two different lasers, $SHG-YVO_4$ (${\lambda}=0.532{\mu}m$) and YAG (${\lambda}=1.064{\mu}m$). The mini-modules are formed through several scribed lines such as pattern-l (front TCO), pattern-2 (PV layers) and pattern-3 (BR/back contact). However, in the case of pattern-3, a high-energy part of laser shot damaged the textured surface of the front TCO, so that the resistance between the each cells decreases due to an incomplete isolation. In this study, the re-deposition of SnOx from the front TCO, Zn (BR layer) and Al (back contact) on the sidewalls of pattern-3 scribed lines was observed. Moreover, re-crystallization of a-Si:H layers due to thermal damage by laser patterning was evaluated. These cause an increase of a leakage current, result in a low efficiency of module. To optimize a-Si:H single junction thin film modules, a laser beam profile was changed, and its effect on isolation of scribed lines is discussed in this paper.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1998년도 PROCEEDINGS OF THE 14TH KACG TECHNICAL MEETING AND THE 5TH KOREA-JAPAN EMGS (ELECTRONIC MATERIALS GROWTH SYMPOSIUM)
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• pp.145-148
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• 1998

Fluoride({{{{ { CaF}_{2 } }}}}) films exhibited a cubic structure with similar lattice constant to that of Si and have sufficient breakdown electric field as gate dielectric material. Therefore, {{{{ { CaF}_{2 } }}}} are expected to replace conventional insulator such {{{{ { SiO}_{ 2},{Ta}_{2}{O}_{ 2} and{Al}_{2}{O}_{5}. However, {CaF}_{2}}}}} films showed hystereisis properties due to mobile charges in the film. To solve this problem we performed thermal treatment and achieves field. C-v results indicate a reduced hystereisis window of {{{{ }}}}ΔV =0.2v, LOW INTERFACE STATE {{{{{D}_{it}=2.0 TIMES {10}^{11}{cm}^{-1}{eV}^{-1}}}}} in midgap, and good WIS diode properties. We observed a preferential crystallization of(200) plane from XRD analysis. RTA treatment effects on various material properties of {{{{{CaF}_{2}}}}} are presented in this paper.

• Journal of Information Display
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• 제8권4호
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• pp.15-18
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• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.