• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.54-65
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• 1999

As the integration ratio and operating speed increase, it has become an important problem to estimate the dissipated power during the design procedure to reduce th TTM(time to market). This paper proposed a prediction model for the maximum dissipated power of a CMOS logic gate. This model uses a calculating method. It was constructed by including the characteristics of MOSFETs, the operational characteristics of the gate, and the characteristics of the input signals. As the construction procedure, a maximum power estimation model for CMOS inverter was formed first, And then, a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. We designed several CMOS gates in layout level with $0.6{\mu}m$ design rule to apply both to HSPICE simulation and to the proposed models. The comparison between the two results showed that the gate conversion model and the power estimation model had within 5% and 10% of the relative errors, respectively. Those values show that the proposed models have sufficient accuracies. Also in calculation time, the proposed models were more than 30 times faster than HSPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.85-90
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• 2013

In this paper, 6bit SAR ADC tolerant to ionizing radiation is presented. Radiation tolerance is achieved by using the Dummy Gate Assisted (DGA) MOSFET which was proposed to suppress the leakage current induced by ionizing radiation and its comparing sample is designed with the conventional MOSFET. The designed ADC consists of binary capacitor DAC, dynamic latch comparator, and digital logic and was fabricated using a standard 0.35um CMOS process. Irradiation was performed by Co-60 gamma ray. After the irradiation, ADC designed with the conventional MOSFET did not operate properly. On the contrary, ADC designed with the DGA MOSFET showed a little parametric degradation of which DNL was increased from 0.7LSB to 2.0LSB and INL was increased from 1.8LSB to 3.2LSB. In spite of its parametric degradation, analog to digital conversion in the ADC with DGA MOSFET was found to be possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.1-11
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• 2002

A multi-section DFB-LD shows optical bistability subject to externally injected light signal, then it has potential applications such as wavelength conversion and optical logic gates. In this paper, we have studied the optical bistability in multi-section DFB-LD using split-step time-domain model. It is confirmed that the multi-section DFB-LD, which is excited inhomogeneously, shows bistability. The optical bistable characteristics are investigated when input light is injected into a absorptive region. Simulation results show that multi-section DFB-LD works as a flip-flop depending on the set-reset optical pulse which has a few ns in switching time and a few pj in switching energy, so that it can act as a optical logic device. Besides, if we change the carrier lifetime and the differential gain coefficient, it is expected that the response time of optical output signal can be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.1
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• pp.96-101
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• 2014

Wind power is the fastest growing renewable energy source in the world and it is expected to remain so for some times. Recently, there is a constant need for the reduction of Operational and Maintenance(O&M) costs of Wind Energy Conversion Systems(WECS). The most efficient way of reducing O&M cost would be to utilize CMS(Condition Monitoring System) of WECS. CMS allows for early detection of the deterioration of the wind generator's health, facilitating a proactive action, minimizing downtime, and finally maximizing productivity. There are two types of faults such as mass unbalance and aerodynamic asymmetry which are related to wind turbine's rotor faults. Generally, these faults tend to generate various vibrations. Therefore, in this work a simple fault detection algorithm based on spectrums of vibration signals and simple max-min decision logic is proposed. Furthermore, in order to verify its feasibility, several simulation studies are carried out by using GH-bladed software.

• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1271-1282
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• 2005

Recently, PC-based control is incredibly developed in the industrial control field, but it is difficult for PLC programming in PC. Therefore, I need to develop the softeware PLC, which support the international PLC programming standard(IECl131-3) and can be applied to diverse control system by using C language. In this paper, I have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user which is used over $90\%$ among the 5 PLC languages, is converted to IL, which is one of intermediate codes, and IL is converted to the standard C rode which can be used in a commercial editor such as Visual C++. In ISPLC, the detection of logical error in high level programming(C) is more eaier than PLC programming itself The study of code conversion of LD->IL->C is firstly tried in the world as well as KOREA. I developed an execution engine with a good practical application. To show the effectiveness of the developed system, 1 applied it to a practical case, a real time traffic control(RT-TC) system. ISPLC is minimized the error debugging and programming time owing to be supported by windows application program.

• Korean Institute of Interior Design Journal
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• v.27 no.2
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• pp.175-185
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• 2018

The purpose of this study is to analyze the concept of 'Gradual Differentiation' in parametric design in terms of pure model logic and thus describe the distinctive feature from the previous design method. To meet the purpose, it explores external cases like gradual factor identified in natural phenomenon and artworks and define the inherent model principles into "Self-similarity', "Correlation', and 'Temporality' by examining these features in terms of algorithm. Meanwhile, it identified the principle of gradual model representation in parametric design within a single system called 'Attractor System' by applying these three concepts into specific methods of parametric design, and by interpreting the logical structure through the association among 'Attractor', 'Field', and 'Differentiation'. The creative utilization of parameter shows that gradual model process in parametric design does not mean a passive "conversion process" merely replacing natural parameter with algorithm; rather, it refers to an active "generating process" creating new meanings and value. By continuing this process of conceptual understanding and insight, creative perspective and practical ability to interpret parameter can be improved.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.16 no.4
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• pp.281-292
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• 2016

The proposed scheme is based on the modified perturb and observe (P&O) algorithm combined with the sliding mode technique. A modified P&O algorithm based sliding mode controller is developed to study the effects of partial shade, temperature, and insolation on the performance of maximum power point tracking (MPPT) used in photovoltaic (PV) systems. Under partially shaded conditions and temperature, the energy conversion efficiency of a PV array is very low, leading to significant power losses. Consequently, increasing efficiency by means of MPPT is particularly important. Conventional techniques are easy to implement but produce oscillations at MPP. The proposed method is applied to a model to simulate the performance of the PV system for solar energy usage, which is compared to the conventional methods under non-uniform insolation improving the PV system utilization efficiency and allowing optimization of the system performance. The modified perturb and observe sliding mode controller successfully overcomes the issues presented by non-uniform conditions and tracks the global MPP. Compared to MPPT techniques, the proposed technique is more efficient; it produces less oscillation at MPP in the steady state, and provides more precise tracking.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.2
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• pp.133-138
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• 2002

In this paper, we propose an integrated GUI environment of parallel fuzzy inference system fur pattern classification of remote sensing data. In this, as 4 fuzzy variables in condition part and 104 fuzzy rules are used, a real time and parallel approach is required. For frost fuzzy computation, we use the scan line conversion algorithm to convert lines of each fuzzy linguistic term to the closest integer pixels. We design 4 fuzzy processor unit to be operated in parallel by using FPGA. As a GUI environment, PCI transmission, image data pre-processing, integer pixel mapping and fuzzy membership tuning are considered. This system can be used in a pattern classification system requiring a rapid inference time in a real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.64-68
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• 2005

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.