• Title/Summary/Keyword: context-based coding

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VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC (H.264/AVC를 위한 CAVLC 엔트로피 부/복호화기의 VLSI 설계)

  • Lee Dae-joon;Jeong Yong-jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.5C
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    • pp.371-381
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    • 2005
  • In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

An efficient Pipelined Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 효율적인 Pipelined Arithmetic Encoder)

  • Yun, Jae-Bok;Park, Tae-Geun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.687-690
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    • 2005
  • H.264/AVC에서 압축 효율을 향상시키기 위해 사용된 entropy coding중에 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 하드웨어 복잡도가 높고 bit-serial 과정에서 data dependancy가 존재하기 때문에 빠른 연산이 어렵다. 본 논문에서는 adaptive arithmetic encoder와 정규화 과정을 효율적으로 구성하여 각 입력 심벌이 정규화 과정의 반복횟수에 관계없이 고정된 cycle에 encoding이 되도록 하였다. 제안한 구조는 pipeline으로 구성하기 용이하며, 이 경우 매 cycle에 한 입력 심벌의 encoding이 가능하다.

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VLC Table Selection Method using Prediction Mode in H.264 CAVLC (H.264 CAVLC에서 예측모드를 이용한 VLC 표 선택 방법)

  • Heo, Jin;Ho, Yo-Sung
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.791-792
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    • 2008
  • We present a new algorithm for VLC table prediction in H.264 context-based adaptive variable length coding (CAVLC). Using both the correlation of coding modes and the statistics of the mode distribution in intra and inter frames, we can predict an appropriate VLC table of the given $4{\times}4$ block. Experimental results demonstrate that the proposed algorithm reduces the bit rate about 0.97% on average, compared to the H.264/AVC standard.

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A Simple Coded ARQ for Satellite Broadcasting

  • Liva, Gianluigi;Kissling, Christian;Hausl, Christoph
    • Journal of Communications and Networks
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    • v.12 no.6
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    • pp.577-581
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    • 2010
  • We introduce a novel packet retransmission technique which improves the efficiency of automatic retransmission query (ARQ) protocols in the context of satellite broadcast/multicast systems. The proposed coded ARQ technique, similarly to fountain coding, performs transmission of redundant packets, which are made by linear combinations of the packets composing the source block. Differently from fountain codes, the packets for the linear combinations are selected on the basis of the retransmission requests coming from the user terminals. The selection is performed in a way that, at the terminals, the source packets can be recovered iteratively by means of simple back-substitutions. This work aims at providing a simple and efficient alternative to reliable multicast protocols based on erasure correction coding techniques.

High Efficient Entropy Coding For Edge Image Compression

  • Han, Jong-Woo;Kim, Do-Hyun;Kim, Yoon
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.31-40
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    • 2016
  • In this paper, we analyse the characteristics of the edge image and propose a new entropy coding optimized to the compression of the edge image. The pixel values of the edge image have the Gaussian distribution around '0', and most of the pixel values are '0'. By using this analysis, the Zero Block technique is utilized in spatial domain. And the Intra Prediction Mode of the edge image is similar to the mode of the surrounding blocks or likely to be the Planar Mode or the Horizontal Mode. In this paper, we make use of the MPM technique that produces the Intra Prediction Mode with high probability modes. By utilizing the above properties, we design a new entropy coding method that is suitable for edge image and perform the compression. In case the existing compression techniques are applied to edge image, compression ratio is low and the algorithm is complicated as more than necessity and the running time is very long, because those techniques are based on the natural images. However, the compression ratio and the running time of the proposed technique is high and very short, respectively, because the proposed algorithm is optimized to the compression of the edge image. Experimental results indicate that the proposed algorithm provides better visual and PSNR performance up to 11 times than the JPEG.

Motion Adaptive Lossless Image Compression Algorithm (움직임 적응적인 무손실 영상 압축 알고리즘)

  • Kim, Young-Ro;Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.4
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    • pp.736-739
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    • 2009
  • In this paper, an efficient lossless compression algorithm using motion adaptation is proposed. It is divided into two parts: a motion adaptation based nonlinear predictor part and a residual data coding part. The proposed nonlinear predictor can reduce prediction error by learning from its past prediction errors using motion adaption. The predictor decides the proper selection of the intra and inter prediction values according to the past prediction error. The reduced error is coded by existing context adaptive coding method. Experimental results show that the proposed algorithm has the higher compression ratio than context modeling methods, such as FELICS, CALIC, and JPEG-LS.

Design of a Pipelined Binary Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 파이프라인 이진 산술 부호화기 설계)

  • Yun, Jae-Bok;Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.42-49
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    • 2007
  • CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

Efficient CAVLC Decoder VLSI Design for HD Images (HD급 영상을 효율적으로 복호하기 위한 CAVLC 복호화기 VLSI 설계)

  • Oh, Myung-Seok;Lee, Won-Jae;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.4 s.316
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    • pp.51-59
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    • 2007
  • In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

A Still Image Compression System with a High Quality Text Compression Capability (고 품질 텍스트 압축 기능을 지원하는 정지영상 압축 시스템)

  • Lee, Je-Myung;Lee, Ho-Suk
    • Journal of KIISE:Software and Applications
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    • v.34 no.3
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    • pp.275-302
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    • 2007
  • We propose a novel still image compression system which supports a high quality text compression function. The system segments the text from the image and compresses the text with a high quality. The system shows 48:1 high compression ratio using context-based adaptive binary arithmetic coding. The arithmetic coding performs the high compression by the codeblocks in the bitplane. The input of the system consists of a segmentation mode and a ROI(Region Of Interest) mode. In segmentation mode, the input image is segmented into a foreground consisting of text and a background consisting of the remaining region. In ROI mode, the input image is represented by the region of interest window. The high quality text compression function with a high compression ratio shows that the proposed system can be comparable with the JPEG2000 products. This system also uses gray coding to improve the compression ratio.

Hardware Implementation of HEVC CABAC Context Modeler (HEVC CABAC 문맥 모델러의 하드웨어 구현)

  • Kim, Doohwan;Moon, Jeonhak;Lee, Seongsoo
    • Journal of IKEEE
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    • v.19 no.2
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    • pp.254-259
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    • 2015
  • CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.