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VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC  

Lee Dae-joon (광운대학교 전자통신공학과 실시간구조 연구실)
Jeong Yong-jin (광운대학교)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.5C, 2005 , pp. 371-381 More about this Journal
Abstract
In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.
Keywords
CAVLC; Variable Length Coding; Entropy Coding; H.264; MPEG-4 AVC;
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